X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fef10_impl.h;h=7a00047829dc3f2c4e7c711d4791e27881e70403;hb=45a49cc7e7a589d268e362ee275c399a6640708a;hp=20155f88a8084c7b8ae29b08b7ab7c04b53cb34e;hpb=5858ad96ce3141cb9785258ca2bc90d162ab5006;p=dpdk.git diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h index 20155f88a8..7a00047829 100644 --- a/drivers/net/sfc/base/ef10_impl.h +++ b/drivers/net/sfc/base/ef10_impl.h @@ -11,6 +11,39 @@ extern "C" { #endif +#define EF10_EVQ_MAXNEVS 32768 +#define EF10_EVQ_MINNEVS 512 + +#define EF10_RXQ_MAXNDESCS 4096 +#define EF10_RXQ_MINNDESCS 512 + +#define EF10_TXQ_MINNDESCS 512 + +#define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t)) +#define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t)) +#define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t)) + +/* Number of hardware EVQ buffers (for compile-time resource dimensions) */ +#define EF10_EVQ_MAXNBUFS (64) + +/* Maximum independent of EFX_BUG35388_WORKAROUND. */ +#define EF10_TXQ_MAXNBUFS 8 + +#if EFSYS_OPT_HUNTINGTON +# if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS) +# error "EF10_EVQ_MAXNBUFS too small" +# endif +#endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD +# if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS) +# error "EF10_EVQ_MAXNBUFS too small" +# endif +#endif /* EFSYS_OPT_MEDFORD */ +#if EFSYS_OPT_MEDFORD2 +# if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS) +# error "EF10_EVQ_MAXNBUFS too small" +# endif +#endif /* EFSYS_OPT_MEDFORD2 */ /* Number of hardware PIO buffers (for compile-time resource dimensions) */ #define EF10_MAX_PIOBUF_NBUFS (16) @@ -161,6 +194,16 @@ ef10_intr_fini( /* NIC */ +extern __checkReturn efx_rc_t +efx_mcdi_vadaptor_alloc( + __in efx_nic_t *enp, + __in uint32_t port_id); + +extern __checkReturn efx_rc_t +efx_mcdi_vadaptor_free( + __in efx_nic_t *enp, + __in uint32_t port_id); + extern __checkReturn efx_rc_t ef10_nic_probe( __in efx_nic_t *enp); @@ -190,6 +233,14 @@ extern __checkReturn efx_rc_t ef10_nic_init( __in efx_nic_t *enp); +extern __checkReturn boolean_t +ef10_nic_hw_unavailable( + __in efx_nic_t *enp); + +extern void +ef10_nic_set_hw_unavailable( + __in efx_nic_t *enp); + #if EFSYS_OPT_DIAG extern __checkReturn efx_rc_t @@ -410,6 +461,12 @@ ef10_nvram_partn_size( __in uint32_t partn, __out size_t *sizep); +extern __checkReturn efx_rc_t +ef10_nvram_partn_info( + __in efx_nic_t *enp, + __in uint32_t partn, + __out efx_nvram_info_t * enip); + extern __checkReturn efx_rc_t ef10_nvram_partn_rw_start( __in efx_nic_t *enp, @@ -453,7 +510,7 @@ ef10_nvram_partn_write( __in efx_nic_t *enp, __in uint32_t partn, __in unsigned int offset, - __out_bcount(size) caddr_t data, + __in_bcount(size) caddr_t data, __in size_t size); extern __checkReturn efx_rc_t @@ -477,17 +534,21 @@ ef10_nvram_partn_set_version( extern __checkReturn efx_rc_t ef10_nvram_buffer_validate( - __in efx_nic_t *enp, __in uint32_t partn, __in_bcount(buffer_size) caddr_t bufferp, __in size_t buffer_size); +extern void +ef10_nvram_buffer_init( + __out_bcount(buffer_size) + caddr_t bufferp, + __in size_t buffer_size); + extern __checkReturn efx_rc_t ef10_nvram_buffer_create( - __in efx_nic_t *enp, - __in uint16_t partn_type, - __in_bcount(buffer_size) + __in uint32_t partn_type, + __out_bcount(buffer_size) caddr_t bufferp, __in size_t buffer_size); @@ -515,6 +576,16 @@ ef10_nvram_buffer_find_item( __out uint32_t *startp, __out uint32_t *lengthp); +extern __checkReturn efx_rc_t +ef10_nvram_buffer_peek_item( + __in_bcount(buffer_size) + caddr_t bufferp, + __in size_t buffer_size, + __in uint32_t offset, + __out uint32_t *tagp, + __out uint32_t *lengthp, + __out uint32_t *value_offsetp); + extern __checkReturn efx_rc_t ef10_nvram_buffer_get_item( __in_bcount(buffer_size) @@ -522,9 +593,10 @@ ef10_nvram_buffer_get_item( __in size_t buffer_size, __in uint32_t offset, __in uint32_t length, - __out_bcount_part(item_max_size, *lengthp) - caddr_t itemp, - __in size_t item_max_size, + __out uint32_t *tagp, + __out_bcount_part(value_max_size, *lengthp) + caddr_t valuep, + __in size_t value_max_size, __out uint32_t *lengthp); extern __checkReturn efx_rc_t @@ -533,7 +605,19 @@ ef10_nvram_buffer_insert_item( caddr_t bufferp, __in size_t buffer_size, __in uint32_t offset, - __in_bcount(length) caddr_t keyp, + __in uint32_t tag, + __in_bcount(length) caddr_t valuep, + __in uint32_t length, + __out uint32_t *lengthp); + +extern __checkReturn efx_rc_t +ef10_nvram_buffer_modify_item( + __in_bcount(buffer_size) + caddr_t bufferp, + __in size_t buffer_size, + __in uint32_t offset, + __in uint32_t tag, + __in_bcount(length) caddr_t valuep, __in uint32_t length, __out uint32_t *lengthp); @@ -558,10 +642,7 @@ ef10_nvram_buffer_finish( /* PHY */ typedef struct ef10_link_state_s { - uint32_t els_adv_cap_mask; - uint32_t els_lp_cap_mask; - unsigned int els_fcntl; - efx_link_mode_t els_link_mode; + efx_phy_link_state_t epls; #if EFSYS_OPT_LOOPBACK efx_loopback_type_t els_loopback; #endif @@ -597,6 +678,11 @@ ef10_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip); +extern __checkReturn efx_rc_t +ef10_phy_link_state_get( + __in efx_nic_t *enp, + __out efx_phy_link_state_t *eplsp); + #if EFSYS_OPT_PHY_STATS extern __checkReturn efx_rc_t @@ -756,6 +842,7 @@ extern void ef10_tx_qdesc_tso2_create( __in efx_txq_t *etp, __in uint16_t ipv4_id, + __in uint16_t outer_ipv4_id, __in uint32_t tcp_seq, __in uint16_t tcp_mss, __out_ecount(count) efx_desc_t *edp, @@ -966,13 +1053,15 @@ extern void ef10_rx_qenable( __in efx_rxq_t *erp); +union efx_rxq_type_data_u; + extern __checkReturn efx_rc_t ef10_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, __in efx_rxq_type_t type, - __in uint32_t type_data, + __in_opt const union efx_rxq_type_data_u *type_data, __in efsys_mem_t *esmp, __in size_t ndescs, __in uint32_t id, @@ -1125,11 +1214,12 @@ extern __checkReturn efx_rc_t efx_mcdi_get_port_modes( __in efx_nic_t *enp, __out uint32_t *modesp, - __out_opt uint32_t *current_modep); + __out_opt uint32_t *current_modep, + __out_opt uint32_t *default_modep); extern __checkReturn efx_rc_t ef10_nic_get_port_mode_bandwidth( - __in uint32_t port_mode, + __in efx_nic_t *enp, __out uint32_t *bandwidth_mbpsp); extern __checkReturn efx_rc_t @@ -1166,6 +1256,169 @@ ef10_get_privilege_mask( __in efx_nic_t *enp, __out uint32_t *maskp); +#if EFSYS_OPT_FW_SUBVARIANT_AWARE + +extern __checkReturn efx_rc_t +efx_mcdi_get_nic_global( + __in efx_nic_t *enp, + __in uint32_t key, + __out uint32_t *valuep); + +extern __checkReturn efx_rc_t +efx_mcdi_set_nic_global( + __in efx_nic_t *enp, + __in uint32_t key, + __in uint32_t value); + +#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ + +#if EFSYS_OPT_EVB +extern __checkReturn efx_rc_t +ef10_evb_init( + __in efx_nic_t *enp); + +extern void +ef10_evb_fini( + __in efx_nic_t *enp); + +extern __checkReturn efx_rc_t +ef10_evb_vswitch_alloc( + __in efx_nic_t *enp, + __out efx_vswitch_id_t *vswitch_idp); + + +extern __checkReturn efx_rc_t +ef10_evb_vswitch_free( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id); + +extern __checkReturn efx_rc_t +ef10_evb_vport_alloc( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_type_t vport_type, + __in uint16_t vid, + __in boolean_t vlan_restrict, + __out efx_vport_id_t *vport_idp); + + +extern __checkReturn efx_rc_t +ef10_evb_vport_free( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id); + +extern __checkReturn efx_rc_t +ef10_evb_vport_mac_addr_add( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id, + __in_ecount(6) uint8_t *addrp); + +extern __checkReturn efx_rc_t +ef10_evb_vport_mac_addr_del( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id, + __in_ecount(6) uint8_t *addrp); + +extern __checkReturn efx_rc_t +ef10_evb_vadaptor_alloc( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id); + + +extern __checkReturn efx_rc_t +ef10_evb_vadaptor_free( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id); + +extern __checkReturn efx_rc_t +ef10_evb_vport_assign( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id, + __in uint32_t vf_index); + +extern __checkReturn efx_rc_t +ef10_evb_vport_reconfigure( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id, + __in_opt uint16_t *vidp, + __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp, + __out_opt boolean_t *fn_resetp); + +extern __checkReturn efx_rc_t +ef10_evb_vport_stats( + __in efx_nic_t *enp, + __in efx_vswitch_id_t vswitch_id, + __in efx_vport_id_t vport_id, + __out efsys_mem_t *esmp); + +#endif /* EFSYS_OPT_EVB */ + +#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER +extern __checkReturn efx_rc_t +ef10_proxy_auth_init( + __in efx_nic_t *enp); + +extern void +ef10_proxy_auth_fini( + __in efx_nic_t *enp); + +extern __checkReturn efx_rc_t +ef10_proxy_auth_mc_config( + __in efx_nic_t *enp, + __in efsys_mem_t *request_bufferp, + __in efsys_mem_t *response_bufferp, + __in efsys_mem_t *status_bufferp, + __in uint32_t block_cnt, + __in_ecount(op_count) uint32_t *op_listp, + __in size_t op_count); + +extern __checkReturn efx_rc_t +ef10_proxy_auth_disable( + __in efx_nic_t *enp); + +extern __checkReturn efx_rc_t +ef10_proxy_auth_privilege_modify( + __in efx_nic_t *enp, + __in uint32_t fn_group, + __in uint32_t pf_index, + __in uint32_t vf_index, + __in uint32_t add_privileges_mask, + __in uint32_t remove_privileges_mask); + + __checkReturn efx_rc_t +ef10_proxy_auth_set_privilege_mask( + __in efx_nic_t *enp, + __in uint32_t vf_index, + __in uint32_t mask, + __in uint32_t value); + + __checkReturn efx_rc_t +ef10_proxy_auth_complete_request( + __in efx_nic_t *enp, + __in uint32_t fn_index, + __in uint32_t proxy_result, + __in uint32_t handle); + + __checkReturn efx_rc_t +ef10_proxy_auth_exec_cmd( + __in efx_nic_t *enp, + __inout efx_proxy_cmd_params_t *paramsp); + + __checkReturn efx_rc_t +ef10_proxy_auth_get_privilege_mask( + __in efx_nic_t *enp, + __in uint32_t pf_index, + __in uint32_t vf_index, + __out uint32_t *maskp); + +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ #if EFSYS_OPT_RX_PACKED_STREAM @@ -1186,10 +1439,11 @@ ef10_get_privilege_mask( #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8 /* Minimum space for packet in packed stream mode */ -#define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \ - P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \ - EFX_MAC_PDU_MIN + \ - EFX_RX_PACKED_STREAM_ALIGNMENT, \ +#define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \ + EFX_P2ROUNDUP(size_t, \ + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \ + EFX_MAC_PDU_MIN + \ + EFX_RX_PACKED_STREAM_ALIGNMENT, \ EFX_RX_PACKED_STREAM_ALIGNMENT) /* Maximum number of credits */ @@ -1197,6 +1451,16 @@ ef10_get_privilege_mask( #endif /* EFSYS_OPT_RX_PACKED_STREAM */ +#if EFSYS_OPT_RX_ES_SUPER_BUFFER + +/* + * Maximum DMA length and buffer stride alignment. + * (see SF-119419-TC, 3.2) + */ +#define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64 + +#endif + #ifdef __cplusplus } #endif