X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fef10_nic.c;h=bab4412feab6ce4a93caf1e9356740135a2d8055;hb=e05af47fd579181ebfdf1357065ded75ceb7ab6e;hp=e37a2acb80ca1a0342109da8b1e1bffd5c70b957;hpb=01a22b15b4cbcc65552ff5ba88ea2d8905bbb7ab;p=dpdk.git diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index e37a2acb80..bab4412fea 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -1175,6 +1175,37 @@ ef10_get_datapath_caps( encp->enc_tunnel_config_udp_entries_max = 0; } + /* + * Check if firmware reports the VI window mode. + * Medford2 has a variable VI window size (8K, 16K or 64K). + * Medford and Huntington have a fixed 8K VI window size. + */ + if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { + uint8_t mode = + MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); + + switch (mode) { + case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K: + encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; + break; + case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K: + encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K; + break; + case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K: + encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K; + break; + default: + encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; + break; + } + } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) || + (enp->en_family == EFX_FAMILY_MEDFORD)) { + /* Huntington and Medford have fixed 8K window size */ + encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; + } else { + encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; + } + /* Check if firmware supports extended MAC stats. */ if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { /* Extended stats buffer supported */ @@ -1207,71 +1238,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t -ef10_get_vi_window_shift( - __in efx_nic_t *enp, - __out uint32_t *vi_window_shiftp) -{ - efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN, - MC_CMD_GET_CAPABILITIES_V3_OUT_LEN)]; - uint32_t mode; - efx_rc_t rc; - - (void) memset(payload, 0, sizeof (payload)); - req.emr_cmd = MC_CMD_GET_CAPABILITIES; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_GET_CAPABILITIES_V3_OUT_LEN; - - efx_mcdi_execute_quiet(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { - rc = EMSGSIZE; - goto fail2; - } - mode = MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); - - switch (mode) { - case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K: - EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8 * 1024); - *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_8K; - break; - - case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K: - EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_16K == 16 * 1024); - *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_16K; - break; - - case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K: - EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_64K == 64 * 1024); - *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_64K; - break; - - default: - *vi_window_shiftp = EFX_VI_WINDOW_SHIFT_INVALID; - rc = EINVAL; - goto fail3; - } - - return (0); - -fail3: - EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, efx_rc_t, rc); - - return (rc); -} - #define EF10_LEGACY_PF_PRIVILEGE_MASK \ (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ @@ -1379,11 +1345,29 @@ static struct ef10_external_port_map_s { */ { EFX_FAMILY_HUNTINGTON, - (1 << TLV_PORT_MODE_10G) | - (1 << TLV_PORT_MODE_10G_10G) | - (1 << TLV_PORT_MODE_10G_10G_10G_10G), - 1, - 1 + (1U << TLV_PORT_MODE_10G) | /* mode 0 */ + (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */ + (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */ + 1, /* ports per cage */ + 1 /* first cage */ + }, + /* + * Modes which for Huntington identify a chip variant where 2 + * adjacent port numbers map to each cage. + * SFN7x42Q (Monza): + * port 0 -> cage 1 + * port 1 -> cage 1 + * port 2 -> cage 2 + * port 3 -> cage 2 + */ + { + EFX_FAMILY_HUNTINGTON, + (1U << TLV_PORT_MODE_40G) | /* mode 1 */ + (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */ + (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */ + (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */ + 2, /* ports per cage */ + 1 /* first cage */ }, /* * Modes that on Medford allocate each port number to a separate @@ -1395,49 +1379,120 @@ static struct ef10_external_port_map_s { */ { EFX_FAMILY_MEDFORD, - (1 << TLV_PORT_MODE_10G) | - (1 << TLV_PORT_MODE_10G_10G), - 1, - 1 + (1U << TLV_PORT_MODE_10G) | /* mode 0 */ + (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */ + 1, /* ports per cage */ + 1 /* first cage */ }, /* - * Modes which for Huntington identify a chip variant where 2 - * adjacent port numbers map to each cage. - * SFN7x42Q (Monza): + * Modes that on Medford allocate 2 adjacent port numbers to each + * cage. * port 0 -> cage 1 * port 1 -> cage 1 * port 2 -> cage 2 * port 3 -> cage 2 */ { - EFX_FAMILY_HUNTINGTON, - (1 << TLV_PORT_MODE_40G) | - (1 << TLV_PORT_MODE_40G_40G) | - (1 << TLV_PORT_MODE_40G_10G_10G) | - (1 << TLV_PORT_MODE_10G_10G_40G), - 2, - 1 + EFX_FAMILY_MEDFORD, + (1U << TLV_PORT_MODE_40G) | /* mode 1 */ + (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */ + (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */ + (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */ + /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */ + (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */ + 2, /* ports per cage */ + 1 /* first cage */ }, /* - * Modes that on Medford allocate 2 adjacent port numbers to each - * cage. + * Modes that on Medford allocate 4 adjacent port numbers to each + * connector, starting on cage 1. * port 0 -> cage 1 * port 1 -> cage 1 + * port 2 -> cage 1 + * port 3 -> cage 1 + */ + { + EFX_FAMILY_MEDFORD, + (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */ + /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */ + (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */ + 4, /* ports per cage */ + 1 /* first cage */ + }, + /* + * Modes that on Medford allocate 4 adjacent port numbers to each + * connector, starting on cage 2. + * port 0 -> cage 2 + * port 1 -> cage 2 * port 2 -> cage 2 * port 3 -> cage 2 */ { EFX_FAMILY_MEDFORD, - (1 << TLV_PORT_MODE_40G) | - (1 << TLV_PORT_MODE_40G_40G) | - (1 << TLV_PORT_MODE_40G_10G_10G) | - (1 << TLV_PORT_MODE_10G_10G_40G) | - (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), - 2, - 1 + (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */ + 4, /* ports per cage */ + 2 /* first cage */ }, /* - * Modes that on Medford allocate 4 adjacent port numbers to each + * Modes that on Medford2 allocate each port number to a separate + * cage. + * port 0 -> cage 1 + * port 1 -> cage 2 + * port 2 -> cage 3 + * port 3 -> cage 4 + */ + { + EFX_FAMILY_MEDFORD2, + (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ + (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ + (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */ + (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */ + (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */ + (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */ + (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */ + 1, /* ports per cage */ + 1 /* first cage */ + }, + /* + * FIXME: Some port modes are not representable in this mapping: + * - TLV_PORT_MODE_1x2_2x1 (mode 17): + * port 0 -> cage 1 + * port 1 -> cage 2 + * port 2 -> cage 2 + */ + /* + * Modes that on Medford2 allocate 2 adjacent port numbers to each + * cage, starting on cage 1. + * port 0 -> cage 1 + * port 1 -> cage 1 + * port 2 -> cage 2 + * port 3 -> cage 2 + */ + { + EFX_FAMILY_MEDFORD2, + (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */ + (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */ + (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */ + (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */ + (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */ + (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */ + 2, /* ports per cage */ + 1 /* first cage */ + }, + /* + * Modes that on Medford2 allocate 2 adjacent port numbers to each + * cage, starting on cage 2. + * port 0 -> cage 2 + * port 1 -> cage 2 + */ + { + EFX_FAMILY_MEDFORD2, + (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */ + 2, /* ports per cage */ + 2 /* first cage */ + }, + /* + * Modes that on Medford2 allocate 4 adjacent port numbers to each * connector, starting on cage 1. * port 0 -> cage 1 * port 1 -> cage 1 @@ -1445,14 +1500,13 @@ static struct ef10_external_port_map_s { * port 3 -> cage 1 */ { - EFX_FAMILY_MEDFORD, - (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) | - (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1), - 4, - 1, + EFX_FAMILY_MEDFORD2, + (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */ + 4, /* ports per cage */ + 1 /* first cage */ }, /* - * Modes that on Medford allocate 4 adjacent port numbers to each + * Modes that on Medford2 allocate 4 adjacent port numbers to each * connector, starting on cage 2. * port 0 -> cage 2 * port 1 -> cage 2 @@ -1460,10 +1514,11 @@ static struct ef10_external_port_map_s { * port 3 -> cage 2 */ { - EFX_FAMILY_MEDFORD, - (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2), - 4, - 2 + EFX_FAMILY_MEDFORD2, + (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */ + (1U << TLV_PORT_MODE_NA_1x2), /* mode 11 */ + 4, /* ports per cage */ + 2 /* first cage */ }, }; @@ -1553,6 +1608,7 @@ ef10_nic_board_cfg( uint32_t board_type = 0; uint32_t base, nvec; uint32_t port; + uint32_t mask; uint32_t pf; uint32_t vf; uint8_t mac_addr[6] = { 0 }; @@ -1680,13 +1736,25 @@ ef10_nic_board_cfg( encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; + /* + * Get the current privilege mask. Note that this may be modified + * dynamically, so this value is informational only. DO NOT use + * the privilege mask to check for sufficient privileges, as that + * can result in time-of-check/time-of-use bugs. + */ + if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) + goto fail10; + encp->enc_privilege_mask = mask; + /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) if (rc != EACCES) - goto fail10; + goto fail11; return (0); +fail11: + EFSYS_PROBE(fail11); fail10: EFSYS_PROBE(fail10); fail9: