X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fef10_tlv_layout.h;h=33b6af095062914cd4849591f3b2773234ee29d1;hb=2048f3a965d85f264ffe62a5dc7b272a85464331;hp=b649008068e2e8ce61f458facb912e1de4efbc39;hpb=d4b89002b0b7792e5fc0f2f9d8d2e4c5489b33b3;p=dpdk.git diff --git a/drivers/net/sfc/base/ef10_tlv_layout.h b/drivers/net/sfc/base/ef10_tlv_layout.h index b649008068..33b6af0950 100644 --- a/drivers/net/sfc/base/ef10_tlv_layout.h +++ b/drivers/net/sfc/base/ef10_tlv_layout.h @@ -4,6 +4,14 @@ * All rights reserved. */ +/* + * This is NOT the original source file. Do NOT edit it. + * To update the tlv layout, please edit the copy in + * the sfregistry repo and then, in that repo, + * "make tlv_headers" or "make export" to + * regenerate and export all types of headers. + */ + /* These structures define the layouts for the TLV items stored in static and * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). * @@ -32,6 +40,8 @@ * 1: dynamic configuration * 2: firmware internal use * 3: license partition + * 4: tsa configuration + * 5: bundle update * * - TTT is a type, which is just a unique value. The same type value * might appear in both locations, indicating a relationship between @@ -77,6 +87,30 @@ #define TLV_TAG_INVALID (0xFFFFFFFF) +/* TLV start. + * + * Marks the start of a TLV layout within a partition that may/may-not be + * a TLV partition. i.e. if a portion of data (at any offset) within a + * partition is expected to be in TLV format, then the first tag in this + * layout is expected to be TLV_TAG_START. + * + * This tag is not used in TLV layouts where the entire partition is TLV. + * Please continue using TLV_TAG_PARTITION_HEADER to indicate the start + * of TLV layout in such cases. + */ + +#define TLV_TAG_START (0xEF10BA5E) + +struct tlv_start { + uint32_t tag; + uint32_t length; + /* Length of the TLV structure following this tag - includes length of all tags + * within the TLV layout starting with this TLV_TAG_START. + * Includes TLV_TAG_END. Does not include TLV_TAG_START + */ + uint32_t tlv_layout_len; +}; + /* TLV partition header. * * In a TLV partition, this must be the first item in the sequence, at offset @@ -407,6 +441,8 @@ struct tlv_firmware_options { #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE +#define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK +#define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP }; /* Voltage settings @@ -500,6 +536,16 @@ struct tlv_pcie_tx_amp_config { uint8_t lane_amp[16]; }; +/* Enum to select an OEM and enable additional functionality related to this OEM + * (e.g. vendor extensions to VPD, NC-SI etc.) */ +#define TLV_TAG_OEM (0x00230000) +struct tlv_oem { + uint32_t tag; + uint32_t length; + uint8_t oem; +}; +#define TLV_OEM_NONE 0 +#define TLV_OEM_DELL 1 /* Global PCIe configuration, second revision. This represents the visible PFs * by a bitmap rather than having the number of the highest visible one. As such @@ -546,6 +592,17 @@ struct tlv_global_port_mode { uint32_t length; uint32_t port_mode; #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ + +/* Huntington port modes */ +#define TLV_PORT_MODE_10G (0) +#define TLV_PORT_MODE_40G (1) +#define TLV_PORT_MODE_10G_10G (2) +#define TLV_PORT_MODE_40G_40G (3) +#define TLV_PORT_MODE_10G_10G_10G_10G (4) +#define TLV_PORT_MODE_40G_10G_10G (6) +#define TLV_PORT_MODE_10G_10G_40G (7) + +/* Medford (and later) port modes */ #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */ #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */ #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */ @@ -553,8 +610,8 @@ struct tlv_global_port_mode { #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */ #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */ #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */ -#define TLV_PORT_MODE_2x1_2x1 (4) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 - WARNING: bug3720: On Newport only, this is actually Quad 10G on mdi0 */ -#define TLV_PORT_MODE_4x1_NA (5) /* Quad 10G/25G on mdi0 */ +#define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */ +#define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */ #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */ #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */ #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */ @@ -565,6 +622,13 @@ struct tlv_global_port_mode { #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */ #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */ #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */ + +/* Snapper-only Medford2 port modes. + * These modes are eftest only, to allow snapper explicit + * selection between multi-channel and LLPCS. In production, + * this selection is automatic and outside world should not + * care about LLPCS. + */ #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */ #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */ #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */ @@ -573,41 +637,13 @@ struct tlv_global_port_mode { #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */ #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL -/* Deprecated aliases */ -#define TLV_PORT_MODE_10G TLV_PORT_MODE_1x1_NA -#define TLV_PORT_MODE_40G TLV_PORT_MODE_1x4_NA -#define TLV_PORT_MODE_10G_10G TLV_PORT_MODE_1x1_1x1 -#define TLV_PORT_MODE_40G_40G TLV_PORT_MODE_1x4_1x4 -#define TLV_PORT_MODE_10G_10G_10G_10G TLV_PORT_MODE_2x1_2x1 -#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 TLV_PORT_MODE_2x1_2x1 /* bug63720: Do not use */ -#define TLV_PORT_MODE_10G_10G_10G_10G_Q TLV_PORT_MODE_4x1_NA -#define TLV_PORT_MODE_40G_10G_10G TLV_PORT_MODE_1x4_2x1 -#define TLV_PORT_MODE_10G_10G_40G TLV_PORT_MODE_2x1_1x4 -#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 TLV_PORT_MODE_NA_4x1 -#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 TLV_PORT_MODE_BUG63720_DO_NOT_USE /* bug63720: Do not use */ -#define TLV_PORT_MODE_25G TLV_PORT_MODE_1x1_NA /* Single 25G on mdi0 */ -#define TLV_PORT_MODE_100G_Q1 TLV_PORT_MODE_1x4_NA /* Single 100G on mdi0 */ -#define TLV_PORT_MODE_100G_Q2 TLV_PORT_MODE_NA_1x4 /* Single 100G on mdi1 */ -#define TLV_PORT_MODE_50G_Q1 TLV_PORT_MODE_1x2_NA /* Single 50G on mdi0 */ -#define TLV_PORT_MODE_50G_Q2 TLV_PORT_MODE_NA_1x2 /* Single 50G on mdi1 */ -#define TLV_PORT_MODE_25G_25G TLV_PORT_MODE_1x1_1x1 /* Single 25G on mdi0, single 25G on mdi1 */ -#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2 TLV_PORT_MODE_2x1_2x1 /* Dual 25G on mdi0, dual 25G on mdi1 */ -#define TLV_PORT_MODE_25G_25G_25G_25G_Q1 TLV_PORT_MODE_4x1_NA /* Quad 25G on mdi0 */ -#define TLV_PORT_MODE_25G_25G_25G_25G_Q2 TLV_PORT_MODE_NA_4x1 /* Quad 25G on mdi1 */ -#define TLV_PORT_MODE_40G_25G_25G TLV_PORT_MODE_1x4_2x1 /* Single 40G on mdi0, dual 25G on mdi1 */ -#define TLV_PORT_MODE_25G_25G_40G TLV_PORT_MODE_2x1_1x4 /* Dual 25G on mdi0, single 40G on mdi1 */ -#define TLV_PORT_MODE_50G_50G_Q1_Q2 TLV_PORT_MODE_1x2_1x2 /* Single 50G on mdi0, single 50G on mdi1 */ -#define TLV_PORT_MODE_50G_50G_Q1 TLV_PORT_MODE_2x2_NA /* Dual 50G on mdi0 */ -#define TLV_PORT_MODE_50G_50G_Q2 TLV_PORT_MODE_NA_2x2 /* Dual 50G on mdi1 */ -#define TLV_PORT_MODE_40G_50G TLV_PORT_MODE_1x4_1x2 /* Single 40G on mdi0, single 50G on mdi1 */ -#define TLV_PORT_MODE_50G_40G TLV_PORT_MODE_1x2_1x4 /* Single 50G on mdi0, single 40G on mdi1 */ -#define TLV_PORT_MODE_50G_25G_25G TLV_PORT_MODE_1x2_2x1 /* Single 50G on mdi0, dual 25G on mdi1 */ -#define TLV_PORT_MODE_25G_25G_50G TLV_PORT_MODE_2x1_1x2 /* Dual 25G on mdi0, single 50G on mdi1 */ -#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */ -#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */ -#define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */ -#define TLV_PORT_MODE_25G_LL TLV_PORT_MODE_1x1_NA_LL /* Single 10G/25G on mdi0, low-latency PCS */ -#define TLV_PORT_MODE_25G_25G_LL TLV_PORT_MODE_1x1_1x1_LL /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */ +/* Deprecated Medford aliases - DO NOT USE IN NEW CODE */ +#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) +#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) +#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) +#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) + +#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL }; /* Type of the v-switch created implicitly by the firmware */ @@ -852,7 +888,7 @@ typedef struct tlv_license { uint8_t data[]; } tlv_license_t; -/* TSA NIC IP address configuration +/* TSA NIC IP address configuration (DEPRECATED) * * Sets the TSA NIC IP address statically via configuration tool or dynamically * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop) @@ -862,7 +898,7 @@ typedef struct tlv_license { * released code yet. */ -#define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) +#define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */ #define TLV_TSAN_IP_MODE_STATIC (0) #define TLV_TSAN_IP_MODE_DHCP (1) @@ -879,7 +915,7 @@ typedef struct tlv_tsan_config { uint32_t bind_bkout; /* DEPRECATED */ } tlv_tsan_config_t; -/* TSA Controller IP address configuration +/* TSA Controller IP address configuration (DEPRECATED) * * Sets the TSA Controller IP address statically via configuration tool * @@ -888,7 +924,7 @@ typedef struct tlv_tsan_config { * released code yet. */ -#define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) +#define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */ #define TLV_MAX_TSACS (4) typedef struct tlv_tsac_config { @@ -899,7 +935,7 @@ typedef struct tlv_tsac_config { uint32_t port[TLV_MAX_TSACS]; } tlv_tsac_config_t; -/* Binding ticket +/* Binding ticket (DEPRECATED) * * Sets the TSA NIC binding ticket used for binding process between the TSA NIC * and the TSA Controller @@ -909,7 +945,7 @@ typedef struct tlv_tsac_config { * released code yet. */ -#define TLV_TAG_TMP_BINDING_TICKET (0x10240000) +#define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */ typedef struct tlv_binding_ticket { uint32_t tag; @@ -934,7 +970,7 @@ typedef struct tlv_pik_sf { uint8_t bytes[]; } tlv_pik_sf_t; -/* CA root certificate +/* CA root certificate (DEPRECATED) * * Sets the CA root certificate used for TSA Controller verfication during * TLS connection setup between the TSA NIC and the TSA Controller @@ -944,7 +980,7 @@ typedef struct tlv_pik_sf { * released code yet. */ -#define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) +#define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */ typedef struct tlv_ca_root_cert { uint32_t tag; @@ -994,4 +1030,34 @@ struct tlv_fastpd_mode { #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */ }; +/* L3xUDP datapath firmware UDP port configuration + * + * Sets the list of UDP ports on which the encapsulation will be handled. + * The number of ports in the list is implied by the length of the TLV item. + */ +#define TLV_TAG_L3XUDP_PORTS (0x102a0000) +struct tlv_l3xudp_ports { + uint32_t tag; + uint32_t length; + uint16_t ports[]; +#define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16 +}; + +/* Wake on LAN setting + * + * Enables the Wake On Lan (WoL) functionality on the given port. This will be + * a persistent setting for manageability firmware. Drivers have direct access + * to WoL using MCDI. + */ +#define TLV_TAG_WAKE_ON_LAN(port) (0x102b0000 + (port)) +struct tlv_wake_on_lan { + uint32_t tag; + uint32_t length; + uint8_t mode; + uint8_t bytes[]; +#define TLV_WAKE_ON_LAN_MODE_DISABLED 0 +#define TLV_WAKE_ON_LAN_MODE_MAGIC_PACKET 1 +#define TLV_WAKE_ON_LAN_MAX_NUM_BYTES 255 +}; + #endif /* CI_MGMT_TLV_LAYOUT_H */