X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fefx.h;h=07cd0bb398ba1a7674739493b9c435f7070007c7;hb=6cf2f95d4dfbae8c8b4ea31ec899e750dcbc62bb;hp=3f862131e71c6d8427fa534dd7d03e1b82f62be6;hpb=373f9fe185df2ead1844f078c0b2155f91902d47;p=dpdk.git diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 3f862131e7..07cd0bb398 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright (c) 2006-2018 Solarflare Communications Inc. - * All rights reserved. + * Copyright(c) 2019-2020 Xilinx, Inc. + * Copyright(c) 2006-2019 Solarflare Communications Inc. */ #ifndef _SYS_EFX_H #define _SYS_EFX_H +#include "efx_annote.h" #include "efsys.h" +#include "efx_types.h" #include "efx_check.h" #include "efx_phy_ids.h" @@ -27,6 +29,18 @@ extern "C" { /* The macro expands divider twice */ #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) +/* Round value up to the nearest power of two. */ +#define EFX_P2ROUNDUP(_type, _value, _align) \ + (-(-(_type)(_value) & -(_type)(_align))) + +/* Align value down to the nearest power of two. */ +#define EFX_P2ALIGN(_type, _value, _align) \ + ((_type)(_value) & -(_type)(_align)) + +/* Test if value is power of 2 aligned. */ +#define EFX_IS_P2ALIGNED(_type, _value, _align) \ + ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) + /* Return codes */ typedef __success(return == 0) int efx_rc_t; @@ -129,9 +143,22 @@ efx_nic_create( __in efsys_lock_t *eslp, __deref_out efx_nic_t **enpp); +/* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ +typedef enum efx_fw_variant_e { + EFX_FW_VARIANT_FULL_FEATURED, + EFX_FW_VARIANT_LOW_LATENCY, + EFX_FW_VARIANT_PACKED_STREAM, + EFX_FW_VARIANT_HIGH_TX_RATE, + EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, + EFX_FW_VARIANT_RULES_ENGINE, + EFX_FW_VARIANT_DPDK, + EFX_FW_VARIANT_DONT_CARE = 0xffffffff +} efx_fw_variant_t; + extern __checkReturn efx_rc_t efx_nic_probe( - __in efx_nic_t *enp); + __in efx_nic_t *enp, + __in efx_fw_variant_t efv); extern __checkReturn efx_rc_t efx_nic_init( @@ -141,6 +168,14 @@ extern __checkReturn efx_rc_t efx_nic_reset( __in efx_nic_t *enp); +extern __checkReturn boolean_t +efx_nic_hw_unavailable( + __in efx_nic_t *enp); + +extern void +efx_nic_set_hw_unavailable( + __in efx_nic_t *enp); + #if EFSYS_OPT_DIAG extern __checkReturn efx_rc_t @@ -187,8 +222,8 @@ efx_nic_check_pcie_link_speed( #if EFSYS_OPT_MCDI -#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 -/* Huntington and Medford require MCDIv2 commands */ +#if EFX_OPTS_EF10() +/* EF10 architecture NICs require MCDIv2 commands */ #define WITH_MCDI_V2 1 #endif @@ -220,6 +255,9 @@ typedef struct efx_mcdi_transport_s { #if EFSYS_OPT_MCDI_PROXY_AUTH void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ +#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER + void (*emt_ev_proxy_request)(void *, uint32_t); +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ } efx_mcdi_transport_t; extern __checkReturn efx_rc_t @@ -278,7 +316,7 @@ extern __checkReturn efx_rc_t efx_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, - __in efsys_mem_t *esmp); + __in_opt efsys_mem_t *esmp); extern void efx_intr_enable( @@ -323,7 +361,7 @@ efx_intr_fini( #if EFSYS_OPT_MAC_STATS -/* START MKCONFIG GENERATED EfxHeaderMacBlock 7b5f45054a3b45bc */ +/* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ typedef enum efx_mac_stat_e { EFX_MAC_RX_OCTETS, EFX_MAC_RX_PKTS, @@ -412,6 +450,25 @@ typedef enum efx_mac_stat_e { EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, + EFX_MAC_CTPIO_VI_BUSY_FALLBACK, + EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, + EFX_MAC_CTPIO_MISSING_DBELL_FAIL, + EFX_MAC_CTPIO_OVERFLOW_FAIL, + EFX_MAC_CTPIO_UNDERFLOW_FAIL, + EFX_MAC_CTPIO_TIMEOUT_FAIL, + EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, + EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, + EFX_MAC_CTPIO_INVALID_WR_FAIL, + EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, + EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, + EFX_MAC_CTPIO_RUNT_FALLBACK, + EFX_MAC_CTPIO_SUCCESS, + EFX_MAC_CTPIO_FALLBACK, + EFX_MAC_CTPIO_POISON, + EFX_MAC_CTPIO_ERASE, + EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, + EFX_MAC_RXDP_HLB_IDLE, + EFX_MAC_RXDP_HLB_TIMEOUT, EFX_MAC_NSTATS } efx_mac_stat_t; @@ -438,6 +495,8 @@ typedef enum efx_link_mode_e { #define EFX_MAC_ADDR_LEN 6 +#define EFX_VNI_OR_VSID_LEN 3 + #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) #define EFX_MAC_MULTICAST_LIST_MAX 256 @@ -451,10 +510,10 @@ typedef enum efx_link_mode_e { + /* bug16011 */ 16) \ #define EFX_MAC_PDU(_sdu) \ - P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) + EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) /* - * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give + * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give * the SDU rounded up slightly. */ #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) @@ -485,6 +544,12 @@ efx_mac_filter_set( __in boolean_t all_mulcst, __in boolean_t brdcst); +extern void +efx_mac_filter_get_all_ucast_mcast( + __in efx_nic_t *enp, + __out boolean_t *all_unicst, + __out boolean_t *all_mulcst); + extern __checkReturn efx_rc_t efx_mac_multicast_list_set( __in efx_nic_t *enp, @@ -540,8 +605,9 @@ efx_mac_stat_name( #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) -#define EFX_MAC_STATS_MASK_NPAGES \ - (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ +#define EFX_MAC_STATS_MASK_NPAGES \ + (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ + EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ EFX_MAC_STATS_MASK_BITS_PER_PAGE) /* @@ -627,77 +693,74 @@ efx_mon_init( #define EFX_MON_STATS_PAGE_SIZE 0x100 #define EFX_MON_MASK_ELEMENT_SIZE 32 -/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */ +/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ typedef enum efx_mon_stat_e { - EFX_MON_STAT_2_5V, - EFX_MON_STAT_VCCP1, - EFX_MON_STAT_VCC, - EFX_MON_STAT_5V, - EFX_MON_STAT_12V, - EFX_MON_STAT_VCCP2, - EFX_MON_STAT_EXT_TEMP, - EFX_MON_STAT_INT_TEMP, - EFX_MON_STAT_AIN1, - EFX_MON_STAT_AIN2, - EFX_MON_STAT_INT_COOLING, - EFX_MON_STAT_EXT_COOLING, - EFX_MON_STAT_1V, - EFX_MON_STAT_1_2V, - EFX_MON_STAT_1_8V, - EFX_MON_STAT_3_3V, - EFX_MON_STAT_1_2VA, - EFX_MON_STAT_VREF, - EFX_MON_STAT_VAOE, + EFX_MON_STAT_CONTROLLER_TEMP, + EFX_MON_STAT_PHY_COMMON_TEMP, + EFX_MON_STAT_CONTROLLER_COOLING, + EFX_MON_STAT_PHY0_TEMP, + EFX_MON_STAT_PHY0_COOLING, + EFX_MON_STAT_PHY1_TEMP, + EFX_MON_STAT_PHY1_COOLING, + EFX_MON_STAT_IN_1V0, + EFX_MON_STAT_IN_1V2, + EFX_MON_STAT_IN_1V8, + EFX_MON_STAT_IN_2V5, + EFX_MON_STAT_IN_3V3, + EFX_MON_STAT_IN_12V0, + EFX_MON_STAT_IN_1V2A, + EFX_MON_STAT_IN_VREF, + EFX_MON_STAT_OUT_VAOE, EFX_MON_STAT_AOE_TEMP, EFX_MON_STAT_PSU_AOE_TEMP, EFX_MON_STAT_PSU_TEMP, - EFX_MON_STAT_FAN0, - EFX_MON_STAT_FAN1, - EFX_MON_STAT_FAN2, - EFX_MON_STAT_FAN3, - EFX_MON_STAT_FAN4, - EFX_MON_STAT_VAOE_IN, - EFX_MON_STAT_IAOE, - EFX_MON_STAT_IAOE_IN, + EFX_MON_STAT_FAN_0, + EFX_MON_STAT_FAN_1, + EFX_MON_STAT_FAN_2, + EFX_MON_STAT_FAN_3, + EFX_MON_STAT_FAN_4, + EFX_MON_STAT_IN_VAOE, + EFX_MON_STAT_OUT_IAOE, + EFX_MON_STAT_IN_IAOE, EFX_MON_STAT_NIC_POWER, - EFX_MON_STAT_0_9V, - EFX_MON_STAT_I0_9V, - EFX_MON_STAT_I1_2V, - EFX_MON_STAT_0_9V_ADC, - EFX_MON_STAT_INT_TEMP2, - EFX_MON_STAT_VREG_TEMP, - EFX_MON_STAT_VREG_0_9V_TEMP, - EFX_MON_STAT_VREG_1_2V_TEMP, - EFX_MON_STAT_INT_VPTAT, - EFX_MON_STAT_INT_ADC_TEMP, - EFX_MON_STAT_EXT_VPTAT, - EFX_MON_STAT_EXT_ADC_TEMP, + EFX_MON_STAT_IN_0V9, + EFX_MON_STAT_IN_I0V9, + EFX_MON_STAT_IN_I1V2, + EFX_MON_STAT_IN_0V9_ADC, + EFX_MON_STAT_CONTROLLER_2_TEMP, + EFX_MON_STAT_VREG_INTERNAL_TEMP, + EFX_MON_STAT_VREG_0V9_TEMP, + EFX_MON_STAT_VREG_1V2_TEMP, + EFX_MON_STAT_CONTROLLER_VPTAT, + EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, + EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, + EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, EFX_MON_STAT_AMBIENT_TEMP, EFX_MON_STAT_AIRFLOW, EFX_MON_STAT_VDD08D_VSS08D_CSR, EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, EFX_MON_STAT_HOTPOINT_TEMP, - EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, - EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, + EFX_MON_STAT_PHY_POWER_PORT0, + EFX_MON_STAT_PHY_POWER_PORT1, EFX_MON_STAT_MUM_VCC, - EFX_MON_STAT_0V9_A, - EFX_MON_STAT_I0V9_A, - EFX_MON_STAT_0V9_A_TEMP, - EFX_MON_STAT_0V9_B, - EFX_MON_STAT_I0V9_B, - EFX_MON_STAT_0V9_B_TEMP, + EFX_MON_STAT_IN_0V9_A, + EFX_MON_STAT_IN_I0V9_A, + EFX_MON_STAT_VREG_0V9_A_TEMP, + EFX_MON_STAT_IN_0V9_B, + EFX_MON_STAT_IN_I0V9_B, + EFX_MON_STAT_VREG_0V9_B_TEMP, EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, - EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, + EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, - EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, + EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, - EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, - EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, + EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, + EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, - EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, - EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, + EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, + EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, EFX_MON_STAT_SODIMM_VOUT, EFX_MON_STAT_SODIMM_0_TEMP, EFX_MON_STAT_SODIMM_1_TEMP, @@ -706,12 +769,12 @@ typedef enum efx_mon_stat_e { EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, EFX_MON_STAT_BOARD_FRONT_TEMP, EFX_MON_STAT_BOARD_BACK_TEMP, - EFX_MON_STAT_I1V8, - EFX_MON_STAT_I2V5, - EFX_MON_STAT_I3V3, - EFX_MON_STAT_I12V0, - EFX_MON_STAT_1_3V, - EFX_MON_STAT_I1V3, + EFX_MON_STAT_IN_I1V8, + EFX_MON_STAT_IN_I2V5, + EFX_MON_STAT_IN_I3V3, + EFX_MON_STAT_IN_I12V0, + EFX_MON_STAT_IN_1V3, + EFX_MON_STAT_IN_I1V3, EFX_MON_NSTATS } efx_mon_stat_t; @@ -725,11 +788,40 @@ typedef enum efx_mon_stat_state_e { EFX_MON_STAT_STATE_NO_READING = 4, } efx_mon_stat_state_t; +typedef enum efx_mon_stat_unit_e { + EFX_MON_STAT_UNIT_UNKNOWN = 0, + EFX_MON_STAT_UNIT_BOOL, + EFX_MON_STAT_UNIT_TEMP_C, + EFX_MON_STAT_UNIT_VOLTAGE_MV, + EFX_MON_STAT_UNIT_CURRENT_MA, + EFX_MON_STAT_UNIT_POWER_W, + EFX_MON_STAT_UNIT_RPM, + EFX_MON_NUNITS +} efx_mon_stat_unit_t; + typedef struct efx_mon_stat_value_s { - uint16_t emsv_value; - uint16_t emsv_state; + uint16_t emsv_value; + efx_mon_stat_state_t emsv_state; + efx_mon_stat_unit_t emsv_unit; } efx_mon_stat_value_t; +typedef struct efx_mon_limit_value_s { + uint16_t emlv_warning_min; + uint16_t emlv_warning_max; + uint16_t emlv_fatal_min; + uint16_t emlv_fatal_max; +} efx_mon_stat_limits_t; + +typedef enum efx_mon_stat_portmask_e { + EFX_MON_STAT_PORTMAP_NONE = 0, + EFX_MON_STAT_PORTMAP_PORT0 = 1, + EFX_MON_STAT_PORTMAP_PORT1 = 2, + EFX_MON_STAT_PORTMAP_PORT2 = 3, + EFX_MON_STAT_PORTMAP_PORT3 = 4, + EFX_MON_STAT_PORTMAP_ALL = (-1), + EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) +} efx_mon_stat_portmask_t; + #if EFSYS_OPT_NAMES extern const char * @@ -737,14 +829,39 @@ efx_mon_stat_name( __in efx_nic_t *enp, __in efx_mon_stat_t id); +extern const char * +efx_mon_stat_description( + __in efx_nic_t *enp, + __in efx_mon_stat_t id); + #endif /* EFSYS_OPT_NAMES */ +extern __checkReturn boolean_t +efx_mon_mcdi_to_efx_stat( + __in int mcdi_index, + __out efx_mon_stat_t *statp); + +extern __checkReturn boolean_t +efx_mon_get_stat_unit( + __in efx_mon_stat_t stat, + __out efx_mon_stat_unit_t *unitp); + +extern __checkReturn boolean_t +efx_mon_get_stat_portmap( + __in efx_mon_stat_t stat, + __out efx_mon_stat_portmask_t *maskp); + extern __checkReturn efx_rc_t efx_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); +extern __checkReturn efx_rc_t +efx_mon_limits_update( + __in efx_nic_t *enp, + __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); + #endif /* EFSYS_OPT_MON_STATS */ extern void @@ -936,12 +1053,39 @@ efx_phy_media_type_get( __in efx_nic_t *enp, __out efx_phy_media_type_t *typep); +/* + * 2-wire device address of the base information in accordance with SFF-8472 + * Diagnostic Monitoring Interface for Optical Transceivers section + * 4 Memory Organization. + */ +#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 + +/* + * 2-wire device address of the digital diagnostics monitoring interface + * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical + * Transceivers section 4 Memory Organization. + */ +#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 + +/* + * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 + * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and + * Operation. + */ +#define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 + +/* + * Maximum accessible data offset for PHY module information. + */ +#define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 + + extern __checkReturn efx_rc_t efx_phy_module_get_info( __in efx_nic_t *enp, __in uint8_t dev_addr, - __in uint8_t offset, - __in uint8_t len, + __in size_t offset, + __in size_t len, __out_bcount(len) uint8_t *data); #if EFSYS_OPT_PHY_STATS @@ -1112,6 +1256,7 @@ efx_bist_stop( #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 #define EFX_FEATURE_PACKED_STREAM 0x00004000 +#define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 typedef enum efx_tunnel_protocol_e { EFX_TUNNEL_PROTOCOL_NONE = 0, @@ -1149,7 +1294,12 @@ typedef struct efx_nic_cfg_s { uint32_t enc_evq_limit; uint32_t enc_txq_limit; uint32_t enc_rxq_limit; + uint32_t enc_evq_max_nevs; + uint32_t enc_evq_min_nevs; + uint32_t enc_rxq_max_ndescs; + uint32_t enc_rxq_min_ndescs; uint32_t enc_txq_max_ndescs; + uint32_t enc_txq_min_ndescs; uint32_t enc_buftbl_limit; uint32_t enc_piobuf_limit; uint32_t enc_piobuf_size; @@ -1157,10 +1307,26 @@ typedef struct efx_nic_cfg_s { uint32_t enc_evq_timer_quantum_ns; uint32_t enc_evq_timer_max_us; uint32_t enc_clk_mult; + uint32_t enc_ev_desc_size; + uint32_t enc_rx_desc_size; + uint32_t enc_tx_desc_size; uint32_t enc_rx_prefix_size; uint32_t enc_rx_buf_align_start; uint32_t enc_rx_buf_align_end; +#if EFSYS_OPT_RX_SCALE uint32_t enc_rx_scale_max_exclusive_contexts; + /* + * Mask of supported hash algorithms. + * Hash algorithm types are used as the bit indices. + */ + uint32_t enc_rx_scale_hash_alg_mask; + /* + * Indicates whether port numbers can be included to the + * input data for hash computation. + */ + boolean_t enc_rx_scale_l4_hash_supported; + boolean_t enc_rx_scale_additional_modes_supported; +#endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_LOOPBACK efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; #endif /* EFSYS_OPT_LOOPBACK */ @@ -1186,15 +1352,16 @@ typedef struct efx_nic_cfg_s { #if EFSYS_OPT_BIST uint32_t enc_bist_mask; #endif /* EFSYS_OPT_BIST */ -#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 +#if EFX_OPTS_EF10() uint32_t enc_pf; uint32_t enc_vf; uint32_t enc_privilege_mask; -#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ +#endif /* EFX_OPTS_EF10() */ boolean_t enc_bug26807_workaround; boolean_t enc_bug35388_workaround; boolean_t enc_bug41750_workaround; boolean_t enc_bug61265_workaround; + boolean_t enc_bug61297_workaround; boolean_t enc_rx_batching_enabled; /* Maximum number of descriptors completed in an rx event. */ uint32_t enc_rx_batch_max; @@ -1214,6 +1381,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_tx_tso_tcp_header_offset_limit; boolean_t enc_fw_assisted_tso_enabled; boolean_t enc_fw_assisted_tso_v2_enabled; + boolean_t enc_fw_assisted_tso_v2_encap_enabled; /* Number of TSO contexts on the NIC (FATSOv2) */ uint32_t enc_fw_assisted_tso_v2_n_contexts; boolean_t enc_hw_tx_insert_vlan_enabled; @@ -1221,12 +1389,18 @@ typedef struct efx_nic_cfg_s { uint32_t enc_hw_pf_count; /* Datapath firmware vadapter/vport/vswitch support */ boolean_t enc_datapath_cap_evb; + /* Datapath firmware vport reconfigure support */ + boolean_t enc_vport_reconfigure_supported; boolean_t enc_rx_disable_scatter_supported; boolean_t enc_allow_set_mac_with_installed_filters; boolean_t enc_enhanced_set_mac_supported; boolean_t enc_init_evq_v2_supported; + boolean_t enc_no_cont_ev_mode_supported; + boolean_t enc_init_rxq_with_buffer_size; boolean_t enc_rx_packed_stream_supported; boolean_t enc_rx_var_packed_stream_supported; + boolean_t enc_rx_es_super_buffer_supported; + boolean_t enc_fw_subvariant_no_tx_csum_supported; boolean_t enc_pm_and_rxdp_counters; boolean_t enc_mac_stats_40g_tx_size_bins; uint32_t enc_tunnel_encapsulations_supported; @@ -1244,12 +1418,26 @@ typedef struct efx_nic_cfg_s { uint32_t enc_required_pcie_bandwidth_mbps; uint32_t enc_max_pcie_link_gen; /* Firmware verifies integrity of NVRAM updates */ - uint32_t enc_nvram_update_verify_result_supported; + boolean_t enc_nvram_update_verify_result_supported; + /* Firmware supports polled NVRAM updates on select partitions */ + boolean_t enc_nvram_update_poll_verify_result_supported; + /* Firmware accepts updates via the BUNDLE partition */ + boolean_t enc_nvram_bundle_update_supported; /* Firmware support for extended MAC_STATS buffer */ uint32_t enc_mac_stats_nstats; boolean_t enc_fec_counters; + boolean_t enc_hlb_counters; + /* Firmware support for "FLAG" and "MARK" filter actions */ + boolean_t enc_filter_action_flag_supported; + boolean_t enc_filter_action_mark_supported; + uint32_t enc_filter_action_mark_max; + /* Port assigned to this PCI function */ + uint32_t enc_assigned_port; } efx_nic_cfg_t; +#define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ + ((configp)->evc_function == 0xffff) + #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) @@ -1260,7 +1448,14 @@ typedef struct efx_nic_cfg_s { extern const efx_nic_cfg_t * efx_nic_cfg_get( - __in efx_nic_t *enp); + __in const efx_nic_t *enp); + +/* RxDPCPU firmware id values by which FW variant can be identified */ +#define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 +#define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 +#define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 +#define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 +#define EFX_RXDP_DPDK_FW_ID 0x6 typedef struct efx_nic_fw_info_s { /* Basic FW version information */ @@ -1301,6 +1496,19 @@ efx_nic_set_drv_limits( __inout efx_nic_t *enp, __in efx_drv_limits_t *edlp); +/* + * Register the OS driver version string for management agents + * (e.g. via NC-SI). The content length is provided (i.e. no + * NUL terminator). Use length 0 to indicate no version string + * should be advertised. It is valid to set the version string + * only before efx_nic_probe() is called. + */ +extern __checkReturn efx_rc_t +efx_nic_set_drv_version( + __inout efx_nic_t *enp, + __in_ecount(length) char const *verp, + __in size_t length); + typedef enum efx_nic_region_e { EFX_REGION_VI, /* Memory BAR UC mapping */ EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ @@ -1423,9 +1631,23 @@ typedef enum efx_nvram_type_e { EFX_NVRAM_LICENSE, EFX_NVRAM_UEFIROM, EFX_NVRAM_MUM_FIRMWARE, + EFX_NVRAM_DYNCONFIG_DEFAULTS, + EFX_NVRAM_ROMCONFIG_DEFAULTS, + EFX_NVRAM_BUNDLE, + EFX_NVRAM_BUNDLE_METADATA, EFX_NVRAM_NTYPES, } efx_nvram_type_t; +typedef struct efx_nvram_info_s { + uint32_t eni_flags; + uint32_t eni_partn_size; + uint32_t eni_address; + uint32_t eni_erase_size; + uint32_t eni_write_size; +} efx_nvram_info_t; + +#define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) + extern __checkReturn efx_rc_t efx_nvram_init( __in efx_nic_t *enp); @@ -1444,6 +1666,12 @@ efx_nvram_size( __in efx_nvram_type_t type, __out size_t *sizep); +extern __checkReturn efx_rc_t +efx_nvram_info( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out efx_nvram_info_t *enip); + extern __checkReturn efx_rc_t efx_nvram_rw_start( __in efx_nic_t *enp, @@ -1548,8 +1776,177 @@ efx_bootcfg_write( __in_bcount(size) uint8_t *data, __in size_t size); + +/* + * Processing routines for buffers arranged in the DHCP/BOOTP option format + * (see https://tools.ietf.org/html/rfc1533) + * + * Summarising the format: the buffer is a sequence of options. All options + * begin with a tag octet, which uniquely identifies the option. Fixed- + * length options without data consist of only a tag octet. Only options PAD + * (0) and END (255) are fixed length. All other options are variable-length + * with a length octet following the tag octet. The value of the length + * octet does not include the two octets specifying the tag and length. The + * length octet is followed by "length" octets of data. + * + * Option data may be a sequence of sub-options in the same format. The data + * content of the encapsulating option is one or more encapsulated sub-options, + * with no terminating END tag is required. + * + * To be valid, the top-level sequence of options should be terminated by an + * END tag. The buffer should be padded with the PAD byte. + * + * When stored to NVRAM, the DHCP option format buffer is preceded by a + * checksum octet. The full buffer (including after the END tag) contributes + * to the checksum, hence the need to fill the buffer to the end with PAD. + */ + +#define EFX_DHCP_END ((uint8_t)0xff) +#define EFX_DHCP_PAD ((uint8_t)0) + +#define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ + (uint16_t)(((encapsulator) << 8) | (encapsulated)) + +extern __checkReturn uint8_t +efx_dhcp_csum( + __in_bcount(size) uint8_t const *data, + __in size_t size); + +extern __checkReturn efx_rc_t +efx_dhcp_verify( + __in_bcount(size) uint8_t const *data, + __in size_t size, + __out_opt size_t *usedp); + +extern __checkReturn efx_rc_t +efx_dhcp_find_tag( + __in_bcount(buffer_length) uint8_t *bufferp, + __in size_t buffer_length, + __in uint16_t opt, + __deref_out uint8_t **valuepp, + __out size_t *value_lengthp); + +extern __checkReturn efx_rc_t +efx_dhcp_find_end( + __in_bcount(buffer_length) uint8_t *bufferp, + __in size_t buffer_length, + __deref_out uint8_t **endpp); + + +extern __checkReturn efx_rc_t +efx_dhcp_delete_tag( + __inout_bcount(buffer_length) uint8_t *bufferp, + __in size_t buffer_length, + __in uint16_t opt); + +extern __checkReturn efx_rc_t +efx_dhcp_add_tag( + __inout_bcount(buffer_length) uint8_t *bufferp, + __in size_t buffer_length, + __in uint16_t opt, + __in_bcount_opt(value_length) uint8_t *valuep, + __in size_t value_length); + +extern __checkReturn efx_rc_t +efx_dhcp_update_tag( + __inout_bcount(buffer_length) uint8_t *bufferp, + __in size_t buffer_length, + __in uint16_t opt, + __in uint8_t *value_locationp, + __in_bcount_opt(value_length) uint8_t *valuep, + __in size_t value_length); + + #endif /* EFSYS_OPT_BOOTCFG */ +#if EFSYS_OPT_IMAGE_LAYOUT + +#include "ef10_signed_image_layout.h" + +/* + * Image header used in unsigned and signed image layouts (see SF-102785-PS). + * + * NOTE: + * The image header format is extensible. However, older drivers require an + * exact match of image header version and header length when validating and + * writing firmware images. + * + * To avoid breaking backward compatibility, we use the upper bits of the + * controller version fields to contain an extra version number used for + * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM + * version). See bug39254 and SF-102785-PS for details. + */ +typedef struct efx_image_header_s { + uint32_t eih_magic; + uint32_t eih_version; + uint32_t eih_type; + uint32_t eih_subtype; + uint32_t eih_code_size; + uint32_t eih_size; + union { + uint32_t eih_controller_version_min; + struct { + uint16_t eih_controller_version_min_short; + uint8_t eih_extra_version_a; + uint8_t eih_extra_version_b; + }; + }; + union { + uint32_t eih_controller_version_max; + struct { + uint16_t eih_controller_version_max_short; + uint8_t eih_extra_version_c; + uint8_t eih_extra_version_d; + }; + }; + uint16_t eih_code_version_a; + uint16_t eih_code_version_b; + uint16_t eih_code_version_c; + uint16_t eih_code_version_d; +} efx_image_header_t; + +#define EFX_IMAGE_HEADER_SIZE (40) +#define EFX_IMAGE_HEADER_VERSION (4) +#define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) + + +typedef struct efx_image_trailer_s { + uint32_t eit_crc; +} efx_image_trailer_t; + +#define EFX_IMAGE_TRAILER_SIZE (4) + +typedef enum efx_image_format_e { + EFX_IMAGE_FORMAT_NO_IMAGE, + EFX_IMAGE_FORMAT_INVALID, + EFX_IMAGE_FORMAT_UNSIGNED, + EFX_IMAGE_FORMAT_SIGNED, + EFX_IMAGE_FORMAT_SIGNED_PACKAGE +} efx_image_format_t; + +typedef struct efx_image_info_s { + efx_image_format_t eii_format; + uint8_t * eii_imagep; + size_t eii_image_size; + efx_image_header_t * eii_headerp; +} efx_image_info_t; + +extern __checkReturn efx_rc_t +efx_check_reflash_image( + __in void *bufferp, + __in uint32_t buffer_size, + __out efx_image_info_t *infop); + +extern __checkReturn efx_rc_t +efx_build_signed_image_write_buffer( + __out_bcount(buffer_size) + uint8_t *bufferp, + __in uint32_t buffer_size, + __in efx_image_info_t *infop, + __out efx_image_header_t **headerpp); + +#endif /* EFSYS_OPT_IMAGE_LAYOUT */ + #if EFSYS_OPT_DIAG typedef enum efx_pattern_type_t { @@ -1598,7 +1995,7 @@ typedef struct efx_evq_s efx_evq_t; #if EFSYS_OPT_QSTATS -/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ +/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ typedef enum efx_ev_qstat_e { EV_ALL, EV_RX, @@ -1637,6 +2034,7 @@ typedef enum efx_ev_qstat_e { EV_DRIVER_TX_DSC_ERROR, EV_DRV_GEN, EV_MCDI_RESPONSE, + EV_RX_PARSE_INCOMPLETE, EV_NQSTATS } efx_ev_qstat_t; @@ -1652,11 +2050,15 @@ extern void efx_ev_fini( __in efx_nic_t *enp); -#define EFX_EVQ_MAXNEVS 32768 -#define EFX_EVQ_MINNEVS 512 +extern __checkReturn size_t +efx_evq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs); -#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) -#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) +extern __checkReturn unsigned int +efx_evq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs); #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) @@ -1667,6 +2069,16 @@ efx_ev_fini( #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ +/* + * Use the NO_CONT_EV RX event format, which allows the firmware to operate more + * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in + * NO_CONT_EV mode". + * + * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, + * which is the case when an event queue is set to THROUGHPUT mode. + */ +#define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) + extern __checkReturn efx_rc_t efx_ev_qcreate( __in efx_nic_t *enp, @@ -1726,7 +2138,7 @@ typedef __checkReturn boolean_t __in uint32_t size, __in uint16_t flags); -#if EFSYS_OPT_RX_PACKED_STREAM +#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER /* * Packed stream mode is documented in SF-112241-TC. @@ -1736,6 +2148,13 @@ typedef __checkReturn boolean_t * packets are put there in a continuous stream. * The main advantage of such an approach is that RX queue refilling * happens much less frequently. + * + * Equal stride packed stream mode is documented in SF-119419-TC. + * The general idea is to utilize advantages of the packed stream, + * but avoid indirection in packets representation. + * The main advantage of such an approach is that RX queue refilling + * happens much less frequently and packets buffers are independent + * from upper layers point of view. */ typedef __checkReturn boolean_t @@ -1836,7 +2255,7 @@ typedef __checkReturn boolean_t typedef struct efx_ev_callbacks_s { efx_initialized_ev_t eec_initialized; efx_rx_ev_t eec_rx; -#if EFSYS_OPT_RX_PACKED_STREAM +#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER efx_rx_ps_ev_t eec_rx_ps; #endif efx_tx_ev_t eec_tx; @@ -1940,15 +2359,36 @@ efx_rx_scatter_enable( typedef enum efx_rx_hash_alg_e { EFX_RX_HASHALG_LFSR = 0, - EFX_RX_HASHALG_TOEPLITZ + EFX_RX_HASHALG_TOEPLITZ, + EFX_RX_HASHALG_PACKED_STREAM, + EFX_RX_NHASHALGS } efx_rx_hash_alg_t; +/* + * Legacy hash type flags. + * + * They represent standard tuples for distinct traffic classes. + */ #define EFX_RX_HASH_IPV4 (1U << 0) #define EFX_RX_HASH_TCPIPV4 (1U << 1) #define EFX_RX_HASH_IPV6 (1U << 2) #define EFX_RX_HASH_TCPIPV6 (1U << 3) -typedef unsigned int efx_rx_hash_type_t; +#define EFX_RX_HASH_LEGACY_MASK \ + (EFX_RX_HASH_IPV4 | \ + EFX_RX_HASH_TCPIPV4 | \ + EFX_RX_HASH_IPV6 | \ + EFX_RX_HASH_TCPIPV6) + +/* + * The type of the argument used by efx_rx_scale_mode_set() to + * provide a means for the client drivers to configure hashing. + * + * A properly constructed value can either be: + * - a combination of legacy flags + * - a combination of EFX_RX_HASH() flags + */ +typedef uint32_t efx_rx_hash_type_t; typedef enum efx_rx_hash_support_e { EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ @@ -1966,6 +2406,93 @@ typedef enum efx_rx_scale_context_type_e { EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ } efx_rx_scale_context_type_t; +/* + * Traffic classes eligible for hash computation. + * + * Select packet headers used in computing the receive hash. + * This uses the same encoding as the RSS_MODES field of + * MC_CMD_RSS_CONTEXT_SET_FLAGS. + */ +#define EFX_RX_CLASS_IPV4_TCP_LBN 8 +#define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 +#define EFX_RX_CLASS_IPV4_UDP_LBN 12 +#define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 +#define EFX_RX_CLASS_IPV4_LBN 16 +#define EFX_RX_CLASS_IPV4_WIDTH 4 +#define EFX_RX_CLASS_IPV6_TCP_LBN 20 +#define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 +#define EFX_RX_CLASS_IPV6_UDP_LBN 24 +#define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 +#define EFX_RX_CLASS_IPV6_LBN 28 +#define EFX_RX_CLASS_IPV6_WIDTH 4 + +#define EFX_RX_NCLASSES 6 + +/* + * Ancillary flags used to construct generic hash tuples. + * This uses the same encoding as RSS_MODE_HASH_SELECTOR. + */ +#define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) +#define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) +#define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) +#define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) + +/* + * Generic hash tuples. + * + * They express combinations of packet fields + * which can contribute to the hash value for + * a particular traffic class. + */ +#define EFX_RX_CLASS_HASH_DISABLE 0 + +#define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR +#define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR + +#define EFX_RX_CLASS_HASH_2TUPLE \ + (EFX_RX_CLASS_HASH_SRC_ADDR | \ + EFX_RX_CLASS_HASH_DST_ADDR) + +#define EFX_RX_CLASS_HASH_2TUPLE_SRC \ + (EFX_RX_CLASS_HASH_SRC_ADDR | \ + EFX_RX_CLASS_HASH_SRC_PORT) + +#define EFX_RX_CLASS_HASH_2TUPLE_DST \ + (EFX_RX_CLASS_HASH_DST_ADDR | \ + EFX_RX_CLASS_HASH_DST_PORT) + +#define EFX_RX_CLASS_HASH_4TUPLE \ + (EFX_RX_CLASS_HASH_SRC_ADDR | \ + EFX_RX_CLASS_HASH_DST_ADDR | \ + EFX_RX_CLASS_HASH_SRC_PORT | \ + EFX_RX_CLASS_HASH_DST_PORT) + +#define EFX_RX_CLASS_HASH_NTUPLES 7 + +/* + * Hash flag constructor. + * + * Resulting flags encode hash tuples for specific traffic classes. + * The client drivers are encouraged to use these flags to form + * a hash type value. + */ +#define EFX_RX_HASH(_class, _tuple) \ + EFX_INSERT_FIELD_NATIVE32(0, 31, \ + EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) + +/* + * The maximum number of EFX_RX_HASH() flags. + */ +#define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) + +extern __checkReturn efx_rc_t +efx_rx_scale_hash_flags_get( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t hash_alg, + __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, + __in unsigned int max_nflags, + __out unsigned int *nflagsp); + extern __checkReturn efx_rc_t efx_rx_hash_default_support_get( __in efx_nic_t *enp, @@ -2025,17 +2552,22 @@ efx_pseudo_hdr_pkt_length_get( __in uint8_t *buffer, __out uint16_t *pkt_lengthp); -#define EFX_RXQ_MAXNDESCS 4096 -#define EFX_RXQ_MINNDESCS 512 +extern __checkReturn size_t +efx_rxq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs); + +extern __checkReturn unsigned int +efx_rxq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs); -#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) -#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) -#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) typedef enum efx_rxq_type_e { EFX_RXQ_TYPE_DEFAULT, EFX_RXQ_TYPE_PACKED_STREAM, + EFX_RXQ_TYPE_ES_SUPER_BUFFER, EFX_RXQ_NTYPES } efx_rxq_type_t; @@ -2061,6 +2593,7 @@ efx_rx_qcreate( __in unsigned int index, __in unsigned int label, __in efx_rxq_type_t type, + __in size_t buf_size, __in efsys_mem_t *esmp, __in size_t ndescs, __in uint32_t id, @@ -2089,6 +2622,28 @@ efx_rx_qcreate_packed_stream( #endif +#if EFSYS_OPT_RX_ES_SUPER_BUFFER + +/* Maximum head-of-line block timeout in nanoseconds */ +#define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) + +extern __checkReturn efx_rc_t +efx_rx_qcreate_es_super_buffer( + __in efx_nic_t *enp, + __in unsigned int index, + __in unsigned int label, + __in uint32_t n_bufs_per_desc, + __in uint32_t max_dma_len, + __in uint32_t buf_stride, + __in uint32_t hol_block_timeout, + __in efsys_mem_t *esmp, + __in size_t ndescs, + __in unsigned int flags, + __in efx_evq_t *eep, + __deref_out efx_rxq_t **erpp); + +#endif + typedef struct efx_buffer_s { efsys_dma_addr_t eb_addr; size_t eb_size; @@ -2168,13 +2723,17 @@ extern void efx_tx_fini( __in efx_nic_t *enp); -#define EFX_TXQ_MINNDESCS 512 +extern __checkReturn size_t +efx_txq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs); -#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) -#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) -#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) +extern __checkReturn unsigned int +efx_txq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs); -#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ +#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) #define EFX_TXQ_CKSUM_IPV4 0x0001 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 @@ -2278,6 +2837,7 @@ extern void efx_tx_qdesc_tso2_create( __in efx_txq_t *etp, __in uint16_t ipv4_id, + __in uint16_t outer_ipv4_id, __in uint32_t tcp_seq, __in uint16_t tcp_mss, __out_ecount(count) efx_desc_t *edp, @@ -2343,6 +2903,10 @@ efx_tx_qdestroy( #define EFX_FILTER_FLAG_RX 0x08 /* Filter is for TX */ #define EFX_FILTER_FLAG_TX 0x10 +/* Set match flag on the received packet */ +#define EFX_FILTER_FLAG_ACTION_FLAG 0x20 +/* Set match mark on the received packet */ +#define EFX_FILTER_FLAG_ACTION_MARK 0x40 typedef uint8_t efx_filter_flags_t; @@ -2371,10 +2935,19 @@ typedef uint8_t efx_filter_flags_t; #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 /* Match by IP transport protocol */ #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 +/* Match by VNI or VSID */ +#define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 +/* For encapsulated packets, match by inner frame local MAC address */ +#define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 /* For encapsulated packets, match all multicast inner frames */ #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 /* For encapsulated packets, match all unicast inner frames */ #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 +/* + * Match by encap type, this flag does not correspond to + * the MCDI match flags and any unoccupied value may be used + */ +#define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 /* Match otherwise-unmatched multicast and broadcast packets */ #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 /* Match otherwise-unmatched unicast packets */ @@ -2382,17 +2955,15 @@ typedef uint8_t efx_filter_flags_t; typedef uint32_t efx_filter_match_flags_t; +/* Filter priority from lowest to highest */ typedef enum efx_filter_priority_s { - EFX_FILTER_PRI_HINT = 0, /* Performance hint */ - EFX_FILTER_PRI_AUTO, /* Automatic filter based on device + EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device * address list or hardware * requirements. This may only be used * by the filter implementation for * each NIC type. */ EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ - EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the - * client (e.g. SR-IOV, HyperV VMQ etc.) - */ + EFX_FILTER_NPRI, } efx_filter_priority_t; /* @@ -2406,6 +2977,13 @@ typedef struct efx_filter_spec_s { efx_filter_flags_t efs_flags; uint16_t efs_dmaq_id; uint32_t efs_rss_context; + uint32_t efs_mark; + /* + * Saved lower-priority filter. If it is set, it is restored on + * filter delete operation. + */ + struct efx_filter_spec_s *efs_overridden_spec; + /* Fields below here are hashed for software filter lookup */ uint16_t efs_outer_vid; uint16_t efs_inner_vid; uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; @@ -2417,6 +2995,8 @@ typedef struct efx_filter_spec_s { uint16_t efs_rem_port; efx_oword_t efs_rem_host; efx_oword_t efs_loc_host; + uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; + uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; } efx_filter_spec_t; @@ -2512,6 +3092,27 @@ efx_filter_spec_set_encap_type( __in efx_tunnel_protocol_t encap_type, __in efx_filter_inner_frame_match_t inner_frame_match); +extern __checkReturn efx_rc_t +efx_filter_spec_set_vxlan( + __inout efx_filter_spec_t *spec, + __in const uint8_t *vni, + __in const uint8_t *inner_addr, + __in const uint8_t *outer_addr); + +extern __checkReturn efx_rc_t +efx_filter_spec_set_geneve( + __inout efx_filter_spec_t *spec, + __in const uint8_t *vni, + __in const uint8_t *inner_addr, + __in const uint8_t *outer_addr); + +extern __checkReturn efx_rc_t +efx_filter_spec_set_nvgre( + __inout efx_filter_spec_t *spec, + __in const uint8_t *vsid, + __in const uint8_t *inner_addr, + __in const uint8_t *outer_addr); + #if EFSYS_OPT_RX_SCALE extern __checkReturn efx_rc_t efx_filter_spec_set_rss_context( @@ -2717,6 +3318,239 @@ efx_tunnel_reconfigure( #endif /* EFSYS_OPT_TUNNEL */ +#if EFSYS_OPT_FW_SUBVARIANT_AWARE + +/** + * Firmware subvariant choice options. + * + * It may be switched to no Tx checksum if attached drivers are either + * preboot or firmware subvariant aware and no VIS are allocated. + * If may be always switched to default explicitly using set request or + * implicitly if unaware driver is attaching. If switching is done when + * a driver is attached, it gets MC_REBOOT event and should recreate its + * datapath. + * + * See SF-119419-TC DPDK Firmware Driver Interface and + * SF-109306-TC EF10 for Driver Writers for details. + */ +typedef enum efx_nic_fw_subvariant_e { + EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, + EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, + EFX_NIC_FW_SUBVARIANT_NTYPES +} efx_nic_fw_subvariant_t; + +extern __checkReturn efx_rc_t +efx_nic_get_fw_subvariant( + __in efx_nic_t *enp, + __out efx_nic_fw_subvariant_t *subvariantp); + +extern __checkReturn efx_rc_t +efx_nic_set_fw_subvariant( + __in efx_nic_t *enp, + __in efx_nic_fw_subvariant_t subvariant); + +#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ + +typedef enum efx_phy_fec_type_e { + EFX_PHY_FEC_NONE = 0, + EFX_PHY_FEC_BASER, + EFX_PHY_FEC_RS +} efx_phy_fec_type_t; + +extern __checkReturn efx_rc_t +efx_phy_fec_type_get( + __in efx_nic_t *enp, + __out efx_phy_fec_type_t *typep); + +typedef struct efx_phy_link_state_s { + uint32_t epls_adv_cap_mask; + uint32_t epls_lp_cap_mask; + uint32_t epls_ld_cap_mask; + unsigned int epls_fcntl; + efx_phy_fec_type_t epls_fec; + efx_link_mode_t epls_link_mode; +} efx_phy_link_state_t; + +extern __checkReturn efx_rc_t +efx_phy_link_state_get( + __in efx_nic_t *enp, + __out efx_phy_link_state_t *eplsp); + + +#if EFSYS_OPT_EVB + +typedef uint32_t efx_vswitch_id_t; +typedef uint32_t efx_vport_id_t; + +typedef enum efx_vswitch_type_e { + EFX_VSWITCH_TYPE_VLAN = 1, + EFX_VSWITCH_TYPE_VEB, + /* VSWITCH_TYPE_VEPA: obsolete */ + EFX_VSWITCH_TYPE_MUX = 4, +} efx_vswitch_type_t; + +typedef enum efx_vport_type_e { + EFX_VPORT_TYPE_NORMAL = 4, + EFX_VPORT_TYPE_EXPANSION, + EFX_VPORT_TYPE_TEST, +} efx_vport_type_t; + +/* Unspecified VLAN ID to support disabling of VLAN filtering */ +#define EFX_FILTER_VID_UNSPEC 0xffff +#define EFX_DEFAULT_VSWITCH_ID 1 + +/* Default VF VLAN ID on creation */ +#define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC +#define EFX_VPORT_ID_INVALID 0 + +typedef struct efx_vport_config_s { + /* Either VF index or 0xffff for PF */ + uint16_t evc_function; + /* VLAN ID of the associated function */ + uint16_t evc_vid; + /* vport id shared with client driver */ + efx_vport_id_t evc_vport_id; + /* MAC address of the associated function */ + uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; + /* + * vports created with this flag set may only transfer traffic on the + * VLANs permitted by the vport. Also, an attempt to install filter with + * VLAN will be refused unless requesting function has VLAN privilege. + */ + boolean_t evc_vlan_restrict; + /* Whether this function is assigned or not */ + boolean_t evc_vport_assigned; +} efx_vport_config_t; + +typedef struct efx_vswitch_s efx_vswitch_t; + +extern __checkReturn efx_rc_t +efx_evb_init( + __in efx_nic_t *enp); + +extern void +efx_evb_fini( + __in efx_nic_t *enp); + +extern __checkReturn efx_rc_t +efx_evb_vswitch_create( + __in efx_nic_t *enp, + __in uint32_t num_vports, + __inout_ecount(num_vports) efx_vport_config_t *vport_configp, + __deref_out efx_vswitch_t **evpp); + +extern __checkReturn efx_rc_t +efx_evb_vswitch_destroy( + __in efx_nic_t *enp, + __in efx_vswitch_t *evp); + +extern __checkReturn efx_rc_t +efx_evb_vport_mac_set( + __in efx_nic_t *enp, + __in efx_vswitch_t *evp, + __in efx_vport_id_t vport_id, + __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); + +extern __checkReturn efx_rc_t +efx_evb_vport_vlan_set( + __in efx_nic_t *enp, + __in efx_vswitch_t *evp, + __in efx_vport_id_t vport_id, + __in uint16_t vid); + +extern __checkReturn efx_rc_t +efx_evb_vport_reset( + __in efx_nic_t *enp, + __in efx_vswitch_t *evp, + __in efx_vport_id_t vport_id, + __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, + __in uint16_t vid, + __out boolean_t *is_fn_resetp); + +extern __checkReturn efx_rc_t +efx_evb_vport_stats( + __in efx_nic_t *enp, + __in efx_vswitch_t *evp, + __in efx_vport_id_t vport_id, + __out efsys_mem_t *stats_bufferp); + +#endif /* EFSYS_OPT_EVB */ + +#if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER + +typedef struct efx_proxy_auth_config_s { + efsys_mem_t *request_bufferp; + efsys_mem_t *response_bufferp; + efsys_mem_t *status_bufferp; + uint32_t block_cnt; + uint32_t *op_listp; + size_t op_count; + uint32_t handled_privileges; +} efx_proxy_auth_config_t; + +typedef struct efx_proxy_cmd_params_s { + uint32_t pf_index; + uint32_t vf_index; + uint8_t *request_bufferp; + size_t request_size; + uint8_t *response_bufferp; + size_t response_size; + size_t *response_size_actualp; +} efx_proxy_cmd_params_t; + +extern __checkReturn efx_rc_t +efx_proxy_auth_init( + __in efx_nic_t *enp); + +extern void +efx_proxy_auth_fini( + __in efx_nic_t *enp); + +extern __checkReturn efx_rc_t +efx_proxy_auth_configure( + __in efx_nic_t *enp, + __in efx_proxy_auth_config_t *configp); + + __checkReturn efx_rc_t +efx_proxy_auth_destroy( + __in efx_nic_t *enp, + __in uint32_t handled_privileges); + + __checkReturn efx_rc_t +efx_proxy_auth_complete_request( + __in efx_nic_t *enp, + __in uint32_t fn_index, + __in uint32_t proxy_result, + __in uint32_t handle); + + __checkReturn efx_rc_t +efx_proxy_auth_exec_cmd( + __in efx_nic_t *enp, + __inout efx_proxy_cmd_params_t *paramsp); + + __checkReturn efx_rc_t +efx_proxy_auth_set_privilege_mask( + __in efx_nic_t *enp, + __in uint32_t vf_index, + __in uint32_t mask, + __in uint32_t value); + + __checkReturn efx_rc_t +efx_proxy_auth_privilege_mask_get( + __in efx_nic_t *enp, + __in uint32_t pf_index, + __in uint32_t vf_index, + __out uint32_t *maskp); + + __checkReturn efx_rc_t +efx_proxy_auth_privilege_modify( + __in efx_nic_t *enp, + __in uint32_t pf_index, + __in uint32_t vf_index, + __in uint32_t add_privileges_mask, + __in uint32_t remove_privileges_mask); + +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ #ifdef __cplusplus }