X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fefx_impl.h;h=46d5389dd45e8f928b9795ba84aa76f0aea74f45;hb=05fa170a2b0760295cb0af687cb1c56c1e6d06ea;hp=78df43018282a342e608d94cefa219c311d2ed1d;hpb=bb5c3b169113773bc932725af0b8c3be3fdcb5eb;p=dpdk.git diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h index 78df430182..46d5389dd4 100644 --- a/drivers/net/sfc/base/efx_impl.h +++ b/drivers/net/sfc/base/efx_impl.h @@ -10,6 +10,9 @@ #include "efx.h" #include "efx_regs.h" #include "efx_regs_ef10.h" +#if EFSYS_OPT_MCDI +#include "efx_mcdi.h" +#endif /* EFSYS_OPT_MCDI */ /* FIXME: Add definition for driver generated software events */ #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV @@ -33,9 +36,9 @@ #include "medford2_impl.h" #endif /* EFSYS_OPT_MEDFORD2 */ -#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) +#if EFX_OPTS_EF10() #include "ef10_impl.h" -#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ +#endif /* EFX_OPTS_EF10() */ #ifdef __cplusplus extern "C" { @@ -55,10 +58,12 @@ extern "C" { #define EFX_MOD_FILTER 0x00001000 #define EFX_MOD_LIC 0x00002000 #define EFX_MOD_TUNNEL 0x00004000 +#define EFX_MOD_EVB 0x00008000 #define EFX_RESET_PHY 0x00000001 #define EFX_RESET_RXQ_ERR 0x00000002 #define EFX_RESET_TXQ_ERR 0x00000004 +#define EFX_RESET_HW_UNAVAIL 0x00000008 typedef enum efx_mac_type_e { EFX_MAC_INVALID = 0, @@ -130,8 +135,9 @@ typedef struct efx_tx_ops_s { } efx_tx_ops_t; typedef union efx_rxq_type_data_u { - /* Dummy member to have non-empty union if no options are enabled */ - uint32_t ertd_dummy; + struct { + size_t ed_buf_size; + } ertd_default; #if EFSYS_OPT_RX_PACKED_STREAM struct { uint32_t eps_buf_size; @@ -223,6 +229,7 @@ typedef struct efx_phy_ops_s { efx_rc_t (*epo_reconfigure)(efx_nic_t *); efx_rc_t (*epo_verify)(efx_nic_t *); efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); + efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); #if EFSYS_OPT_PHY_STATS efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, uint32_t *); @@ -356,6 +363,8 @@ typedef struct efx_nic_ops_s { efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, uint32_t *, size_t *); + boolean_t (*eno_hw_unavailable)(efx_nic_t *); + void (*eno_set_hw_unavailable)(efx_nic_t *); #if EFSYS_OPT_DIAG efx_rc_t (*eno_register_test)(efx_nic_t *); #endif /* EFSYS_OPT_DIAG */ @@ -426,9 +435,9 @@ typedef struct efx_filter_s { #if EFSYS_OPT_SIENA siena_filter_t *ef_siena_filter; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 +#if EFX_OPTS_EF10() ef10_filter_table_t *ef_ef10_filter_table; -#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ +#endif /* EFX_OPTS_EF10() */ } efx_filter_t; #if EFSYS_OPT_SIENA @@ -493,7 +502,8 @@ typedef struct efx_nvram_ops_s { #endif /* EFSYS_OPT_DIAG */ efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, uint32_t *); - efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); + efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, + efx_nvram_info_t *); efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, unsigned int, caddr_t, size_t); @@ -554,10 +564,7 @@ efx_mcdi_nvram_metadata( efx_mcdi_nvram_info( __in efx_nic_t *enp, __in uint32_t partn, - __out_opt size_t *sizep, - __out_opt uint32_t *addressp, - __out_opt uint32_t *erase_sizep, - __out_opt uint32_t *write_sizep); + __out efx_nvram_info_t *eni); __checkReturn efx_rc_t efx_mcdi_nvram_update_start( @@ -588,11 +595,15 @@ efx_mcdi_nvram_write( __in_bcount(size) caddr_t data, __in size_t size); +#define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 +#define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 + __checkReturn efx_rc_t efx_mcdi_nvram_update_finish( __in efx_nic_t *enp, __in uint32_t partn, __in boolean_t reboot, + __in uint32_t flags, __out_opt uint32_t *verify_resultp); #if EFSYS_OPT_DIAG @@ -639,6 +650,49 @@ typedef struct efx_lic_ops_s { #endif +#if EFSYS_OPT_EVB + +struct efx_vswitch_s { + efx_nic_t *ev_enp; + efx_vswitch_id_t ev_vswitch_id; + uint32_t ev_num_vports; + /* + * Vport configuration array: index 0 to store PF configuration + * and next ev_num_vports-1 entries hold VFs configuration. + */ + efx_vport_config_t *ev_evcp; +}; + +typedef struct efx_evb_ops_s { + efx_rc_t (*eeo_init)(efx_nic_t *); + void (*eeo_fini)(efx_nic_t *); + efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); + efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); + efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_type_t, uint16_t, + boolean_t, efx_vport_id_t *); + efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_id_t); + efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_id_t, uint8_t *); + efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_id_t, uint8_t *); + efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_id_t); + efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_id_t); + efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, + efx_vport_id_t, uint32_t); +} efx_evb_ops_t; + +extern __checkReturn boolean_t +efx_is_zero_eth_addr( + __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); + +#endif /* EFSYS_OPT_EVB */ + +#define EFX_DRV_VER_MAX 20 + typedef struct efx_drv_cfg_s { uint32_t edc_min_vi_count; uint32_t edc_max_vi_count; @@ -669,6 +723,7 @@ struct efx_nic_s { const efx_tx_ops_t *en_etxop; const efx_rx_ops_t *en_erxop; efx_fw_variant_t efv; + char en_drv_version[EFX_DRV_VER_MAX]; #if EFSYS_OPT_FILTER efx_filter_t en_filter; const efx_filter_ops_t *en_efop; @@ -712,7 +767,7 @@ struct efx_nic_s { #endif /* EFSYS_OPT_SIENA */ int enu_unused; } en_u; -#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) +#if EFX_OPTS_EF10() union en_arch { struct { int ena_vi_base; @@ -733,9 +788,18 @@ struct efx_nic_s { size_t ena_wc_mem_map_size; } ef10; } en_arch; -#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ +#endif /* EFX_OPTS_EF10() */ +#if EFSYS_OPT_EVB + const efx_evb_ops_t *en_eeop; + struct efx_vswitch_s *en_vswitchp; +#endif /* EFSYS_OPT_EVB */ }; +#define EFX_FAMILY_IS_EF10(_enp) \ + ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ + (_enp)->en_family == EFX_FAMILY_MEDFORD || \ + (_enp)->en_family == EFX_FAMILY_HUNTINGTON) + #define EFX_NIC_MAGIC 0x02121996 @@ -756,6 +820,7 @@ typedef struct efx_evq_rxq_state_s { struct efx_evq_s { uint32_t ee_magic; + uint32_t ee_flags; efx_nic_t *ee_enp; unsigned int ee_index; unsigned int ee_mask; @@ -774,14 +839,22 @@ struct efx_evq_s { #endif /* EFSYS_OPT_MCDI */ efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; - - uint32_t ee_flags; }; #define EFX_EVQ_MAGIC 0x08081997 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ +#if EFSYS_OPT_QSTATS +#define EFX_EV_QSTAT_INCR(_eep, _stat) \ + do { \ + (_eep)->ee_stat[_stat]++; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) +#else +#define EFX_EV_QSTAT_INCR(_eep, _stat) +#endif + struct efx_rxq_s { uint32_t er_magic; efx_nic_t *er_enp; @@ -789,6 +862,7 @@ struct efx_rxq_s { unsigned int er_index; unsigned int er_label; unsigned int er_mask; + size_t er_buf_size; efsys_mem_t *er_esmp; efx_evq_rxq_state_t *er_ev_qstate; };