X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fhunt_nic.c;h=054d4f432f6143f4e397f622094d2be741ca4f11;hb=d6b55d568278316d5da6bdd66f3f8b39771d8950;hp=13f769c2cc6b92a7ed989de85f41965229e2c5a2;hpb=08d38249bc8cd553c9e0268b6d90f07078a6281a;p=dpdk.git diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index 13f769c2cc..054d4f432f 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -20,7 +20,6 @@ hunt_nic_get_required_pcie_bandwidth( __out uint32_t *bandwidth_mbpsp) { uint32_t port_modes; - uint32_t max_port_mode; uint32_t bandwidth; efx_rc_t rc; @@ -30,13 +29,14 @@ hunt_nic_get_required_pcie_bandwidth( * capable mode is in use. */ - if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) { + if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, + NULL, NULL)) != 0) { /* No port mode info available */ bandwidth = 0; goto out; } - if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) { + if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) { /* * This needs the full PCIe bandwidth (and could use * more) - roughly 64 Gbit/s for 8 lanes of Gen3. @@ -45,18 +45,14 @@ hunt_nic_get_required_pcie_bandwidth( EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0) goto fail1; } else { - if (port_modes & (1 << TLV_PORT_MODE_40G)) { - max_port_mode = TLV_PORT_MODE_40G; - } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) { - max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G; + if (port_modes & (1U << TLV_PORT_MODE_40G)) { + bandwidth = 40000; + } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) { + bandwidth = 4 * 10000; } else { /* Assume two 10G ports */ - max_port_mode = TLV_PORT_MODE_10G_10G; + bandwidth = 2 * 10000; } - - if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode, - &bandwidth)) != 0) - goto fail2; } out: @@ -64,8 +60,6 @@ out: return (0); -fail2: - EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, efx_rc_t, rc); @@ -77,49 +71,12 @@ hunt_board_cfg( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t board_type = 0; - ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t mask; uint32_t flags; uint32_t sysclk, dpcpu_clk; - uint32_t base, nvec; uint32_t bandwidth; efx_rc_t rc; - /* Huntington has a fixed 8Kbyte VI window size */ - EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192); - EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192); - EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192); - EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192); - EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192); - - EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); - encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - - /* Board configuration */ - rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); - if (rc != 0) { - /* Unprivileged functions may not be able to read board cfg */ - if (rc == EACCES) - board_type = 0; - else - goto fail1; - } - - encp->enc_board_type = board_type; - encp->enc_clk_mult = 1; /* not used for Huntington */ - - /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ - if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail2; - - /* Obtain the default PHY advertised capabilities */ - if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail3; - epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; - epp->ep_adv_cap_mask = els.els_adv_cap_mask; - /* * Enable firmware workarounds for hardware errata. * Expected responses are: @@ -147,7 +104,7 @@ hunt_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug35388_workaround = B_FALSE; else - goto fail4; + goto fail1; /* * If the bug41750 workaround is enabled, then do not test interrupts, @@ -166,7 +123,7 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug41750_workaround = B_FALSE; } else { - goto fail5; + goto fail2; } if (EFX_PCI_FUNCTION_IS_VF(encp)) { /* Interrupt testing does not work for VFs. See bug50084. */ @@ -204,12 +161,12 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug26807_workaround = B_FALSE; } else { - goto fail6; + goto fail3; } /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail7; + goto fail4; /* * The Huntington timer quantum is 1536 sysclk cycles, documented for @@ -226,81 +183,39 @@ hunt_board_cfg( encp->enc_bug61265_workaround = B_FALSE; /* Medford only */ - /* Check capabilities of running datapath firmware */ - if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail8; + /* Checksums for TSO sends can be incorrect on Huntington. */ + encp->enc_bug61297_workaround = B_TRUE; + + encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; + encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ - /* Alignment for WPTR updates */ - encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; - - /* - * Maximum number of exclusive RSS contexts which can be allocated. The - * hardware supports 64, but 6 are reserved for shared contexts. They - * are a global resource so not all may be available. - */ - encp->enc_rx_scale_max_exclusive_contexts = 58; - - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; + encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; + encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS; - /* - * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use - * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available - * resources (allocated to this PCIe function), which is zero until - * after we have allocated VIs. - */ - encp->enc_evq_limit = 1024; - encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; - encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; + encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; + encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; /* * The workaround for bug35388 uses the top bit of transmit queue * descriptor writes, preventing the use of 4096 descriptor TXQs. */ - encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096; - - encp->enc_buftbl_limit = 0xFFFFFFFF; + encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? + HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND : + HUNT_TXQ_MAXNDESCS; + encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; encp->enc_piobuf_size = HUNT_PIOBUF_SIZE; encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE; - /* - * Get the current privilege mask. Note that this may be modified - * dynamically, so this value is informational only. DO NOT use - * the privilege mask to check for sufficient privileges, as that - * can result in time-of-check/time-of-use bugs. - */ - if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail9; - encp->enc_privilege_mask = mask; - - /* Get interrupt vector limits */ - if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { - if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail10; - - /* Ignore error (cannot query vector limits from a VF). */ - base = 0; - nvec = 1024; - } - encp->enc_intr_vec_base = base; - encp->enc_intr_limit = nvec; - - /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; - if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) - goto fail11; + goto fail5; encp->enc_required_pcie_bandwidth_mbps = bandwidth; /* All Huntington devices have a PCIe Gen3, 8 lane connector */ @@ -308,18 +223,6 @@ hunt_board_cfg( return (0); -fail11: - EFSYS_PROBE(fail11); -fail10: - EFSYS_PROBE(fail10); -fail9: - EFSYS_PROBE(fail9); -fail8: - EFSYS_PROBE(fail8); -fail7: - EFSYS_PROBE(fail7); -fail6: - EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: