X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fhunt_nic.c;h=1e2b075ff277f25b33086e5c0de6f2efee53d176;hb=05fa170a2b0760295cb0af687cb1c56c1e6d06ea;hp=b4fc3cc9efec3422fd5217d6d07d2f635834b4f0;hpb=914e878cd9e7b15b9d285041337b0fb7f8c759d9;p=dpdk.git

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index b4fc3cc9ef..1e2b075ff2 100644
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -72,7 +72,6 @@ hunt_board_cfg(
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_port_t *epp = &(enp->en_port);
-	uint32_t flags;
 	uint32_t sysclk, dpcpu_clk;
 	uint32_t bandwidth;
 	efx_rc_t rc;
@@ -130,43 +129,9 @@ hunt_board_cfg(
 		encp->enc_bug41750_workaround = B_TRUE;
 	}
 
-	/*
-	 * If the bug26807 workaround is enabled, then firmware has enabled
-	 * support for chained multicast filters. Firmware will reset (FLR)
-	 * functions which have filters in the hardware filter table when the
-	 * workaround is enabled/disabled.
-	 *
-	 * We must recheck if the workaround is enabled after inserting the
-	 * first hardware filter, in case it has been changed since this check.
-	 */
-	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
-	    B_TRUE, &flags);
-	if (rc == 0) {
-		encp->enc_bug26807_workaround = B_TRUE;
-		if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
-			/*
-			 * Other functions had installed filters before the
-			 * workaround was enabled, and they have been reset
-			 * by firmware.
-			 */
-			EFSYS_PROBE(bug26807_workaround_flr_done);
-			/* FIXME: bump MC warm boot count ? */
-		}
-	} else if (rc == EACCES) {
-		/*
-		 * Unprivileged functions cannot enable the workaround in older
-		 * firmware.
-		 */
-		encp->enc_bug26807_workaround = B_FALSE;
-	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
-		encp->enc_bug26807_workaround = B_FALSE;
-	} else {
-		goto fail3;
-	}
-
 	/* Get clock frequencies (in MHz). */
 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-		goto fail4;
+		goto fail3;
 
 	/*
 	 * The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -186,6 +151,8 @@ hunt_board_cfg(
 	/* Checksums for TSO sends can be incorrect on Huntington. */
 	encp->enc_bug61297_workaround = B_TRUE;
 
+	encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
+	encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
 	encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
 
 	/* Alignment for receive packet DMA buffers */
@@ -213,7 +180,7 @@ hunt_board_cfg(
 	encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
 
 	if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-		goto fail5;
+		goto fail4;
 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
 	/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -221,8 +188,6 @@ hunt_board_cfg(
 
 	return (0);
 
-fail5:
-	EFSYS_PROBE(fail5);
 fail4:
 	EFSYS_PROBE(fail4);
 fail3: