X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fmedford2_nic.c;h=3efc358865aad1411fd385929a5ebc62dac683ec;hb=e7feaba71c02418796afbe4356840e725ca6df6b;hp=2090990167da5001f1a49f9714fc82c4e2a78b35;hpb=5858ad96ce3141cb9785258ca2bc90d162ab5006;p=dpdk.git

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 2090990167..3efc358865 100644
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -23,7 +23,7 @@ medford2_nic_get_required_pcie_bandwidth(
 	/* FIXME: support new Medford2 dynamic port modes */
 
 	if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
-				    &current_mode)) != 0) {
+				    &current_mode, NULL)) != 0) {
 		/* No port mode info available. */
 		bandwidth = 0;
 		goto out;
@@ -54,11 +54,6 @@ medford2_board_cfg(
 	uint32_t bandwidth;
 	efx_rc_t rc;
 
-	/*
-	 * FIXME: Likely to be incomplete and incorrect.
-	 * Parts of this should be shared with Huntington.
-	 */
-
 	/*
 	 * Enable firmware workarounds for hardware errata.
 	 * Expected responses are:
@@ -101,6 +96,9 @@ medford2_board_cfg(
 	else
 		goto fail1;
 
+	/* Checksums for TSO sends should always be correct on Medford2. */
+	encp->enc_bug61297_workaround = B_FALSE;
+
 	/* Get clock frequencies (in MHz). */
 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
 		goto fail2;