X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fmedford2_nic.c;h=7f5ad17577e84ec4a66bfab7e40e7e7977bf5592;hb=7ed3599095565792cfd0a4de13f1b03be9412f14;hp=1b5690b2e5743abd551ef4d2a1d9331b91e229c6;hpb=9bd777a7e64b8a2e6c88f03327512214f5a8d644;p=dpdk.git

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 1b5690b2e5..7f5ad17577 100644
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -49,27 +49,11 @@ medford2_board_cfg(
 	__in		efx_nic_t *enp)
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-	uint32_t mask;
 	uint32_t sysclk, dpcpu_clk;
-	uint32_t base, nvec;
 	uint32_t end_padding;
 	uint32_t bandwidth;
-	uint32_t vi_window_shift;
 	efx_rc_t rc;
 
-	/*
-	 * FIXME: Likely to be incomplete and incorrect.
-	 * Parts of this should be shared with Huntington.
-	 */
-
-	/* Medford2 has a variable VI window size (8K, 16K or 64K) */
-	if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
-		goto fail1;
-
-	EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
-	encp->enc_vi_window_shift = vi_window_shift;
-
-
 	/*
 	 * Enable firmware workarounds for hardware errata.
 	 * Expected responses are:
@@ -110,11 +94,11 @@ medford2_board_cfg(
 	else if ((rc == ENOTSUP) || (rc == ENOENT))
 		encp->enc_bug61265_workaround = B_FALSE;
 	else
-		goto fail2;
+		goto fail1;
 
 	/* Get clock frequencies (in MHz). */
 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-		goto fail3;
+		goto fail2;
 
 	/*
 	 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -130,23 +114,13 @@ medford2_board_cfg(
 	/* Get the RX DMA end padding alignment configuration */
 	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
 		if (rc != EACCES)
-			goto fail4;
+			goto fail3;
 
 		/* Assume largest tail padding size supported by hardware */
 		end_padding = 256;
 	}
 	encp->enc_rx_buf_align_end = end_padding;
 
-	/*
-	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
-	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
-	 * resources (allocated to this PCIe function), which is zero until
-	 * after we have allocated VIs.
-	 */
-	encp->enc_evq_limit = 1024;
-	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
-	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
-
 	/*
 	 * The maximum supported transmit queue size is 2048. TXQs with 4096
 	 * descriptors are not supported as the top bit is used for vfifo
@@ -154,35 +128,11 @@ medford2_board_cfg(
 	 */
 	encp->enc_txq_max_ndescs = 2048;
 
-	encp->enc_buftbl_limit = 0xFFFFFFFF;
-
 	EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
 	encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
 	encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
 	encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
 
-	/*
-	 * Get the current privilege mask. Note that this may be modified
-	 * dynamically, so this value is informational only. DO NOT use
-	 * the privilege mask to check for sufficient privileges, as that
-	 * can result in time-of-check/time-of-use bugs.
-	 */
-	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-		goto fail5;
-	encp->enc_privilege_mask = mask;
-
-	/* Get interrupt vector limits */
-	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
-		if (EFX_PCI_FUNCTION_IS_PF(encp))
-			goto fail6;
-
-		/* Ignore error (cannot query vector limits from a VF). */
-		base = 0;
-		nvec = 1024;
-	}
-	encp->enc_intr_vec_base = base;
-	encp->enc_intr_limit = nvec;
-
 	/*
 	 * Medford2 stores a single global copy of VPD, not per-PF as on
 	 * Huntington.
@@ -191,18 +141,12 @@ medford2_board_cfg(
 
 	rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
 	if (rc != 0)
-		goto fail7;
+		goto fail4;
 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
 	return (0);
 
-fail7:
-	EFSYS_PROBE(fail7);
-fail6:
-	EFSYS_PROBE(fail6);
-fail5:
-	EFSYS_PROBE(fail5);
 fail4:
 	EFSYS_PROBE(fail4);
 fail3: