X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fbase%2Fmedford_nic.c;h=6c85b0c841fd61a4b9c1d2936e1031ed982ea4c5;hb=d789705873d47d70a3ba0a6a4dfb83fb629d3464;hp=a8812bb866bcce7e2871b395e5e40cb7b7251b5d;hpb=5858ad96ce3141cb9785258ca2bc90d162ab5006;p=dpdk.git diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index a8812bb866..6c85b0c841 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright (c) 2015-2018 Solarflare Communications Inc. - * All rights reserved. + * Copyright(c) 2019-2020 Xilinx, Inc. + * Copyright(c) 2015-2019 Solarflare Communications Inc. */ #include "efx.h" @@ -15,23 +15,13 @@ medford_nic_get_required_pcie_bandwidth( __in efx_nic_t *enp, __out uint32_t *bandwidth_mbpsp) { - uint32_t port_modes; - uint32_t current_mode; uint32_t bandwidth; efx_rc_t rc; - if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, - ¤t_mode)) != 0) { - /* No port mode info available. */ - bandwidth = 0; - goto out; - } - - if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode, + if ((rc = ef10_nic_get_port_mode_bandwidth(enp, &bandwidth)) != 0) goto fail1; -out: *bandwidth_mbpsp = bandwidth; return (0); @@ -52,11 +42,6 @@ medford_board_cfg( uint32_t bandwidth; efx_rc_t rc; - /* - * FIXME: Likely to be incomplete and incorrect. - * Parts of this should be shared with Huntington. - */ - /* * Enable firmware workarounds for hardware errata. * Expected responses are: @@ -82,9 +67,6 @@ medford_board_cfg( encp->enc_bug41750_workaround = B_TRUE; } - /* Chained multicast is always enabled on Medford */ - encp->enc_bug26807_workaround = B_TRUE; - /* * If the bug61265 workaround is enabled, then interrupt holdoff timers * cannot be controlled by timer table writes, so MCDI must be used @@ -99,6 +81,9 @@ medford_board_cfg( else goto fail1; + /* Checksums for TSO sends can be incorrect on Medford. */ + encp->enc_bug61297_workaround = B_TRUE; + /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) goto fail2; @@ -111,6 +96,10 @@ medford_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; + encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; + /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -124,12 +113,19 @@ medford_board_cfg( } encp->enc_rx_buf_align_end = end_padding; + encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; + encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS; + + encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; + encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; + /* * The maximum supported transmit queue size is 2048. TXQs with 4096 * descriptors are not supported as the top bit is used for vfifo * stuffing. */ - encp->enc_txq_max_ndescs = 2048; + encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS; + encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;