X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fsfc_dp_rx.h;h=2101fd7547540164d51cf24438b64771cf3f7949;hb=6cf2f95d4dfbae8c8b4ea31ec899e750dcbc62bb;hp=c3cc4ff5b311e17f21cd3185d013f5a7a3e9869a;hpb=048a0d1a81b64f003d08468c5b18ac3a0406e819;p=dpdk.git

diff --git a/drivers/net/sfc/sfc_dp_rx.h b/drivers/net/sfc/sfc_dp_rx.h
index c3cc4ff5b3..2101fd7547 100644
--- a/drivers/net/sfc/sfc_dp_rx.h
+++ b/drivers/net/sfc/sfc_dp_rx.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright (c) 2017-2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2017-2019 Solarflare Communications Inc.
  *
  * This software was jointly developed between OKTET Labs (under contract
  * for Solarflare) and Solarflare Communications, Inc.
@@ -32,6 +32,8 @@ struct sfc_dp_rxq {
 struct sfc_dp_rx_hw_limits {
 	unsigned int rxq_max_entries;
 	unsigned int rxq_min_entries;
+	unsigned int evq_max_entries;
+	unsigned int evq_min_entries;
 };
 
 /**
@@ -72,6 +74,8 @@ struct sfc_dp_rx_qcreate_info {
 	/** DMA-mapped Rx descriptors ring */
 	void			*rxq_hw_ring;
 
+	/** Event queue index in hardware */
+	unsigned int		evq_hw_index;
 	/** Associated event queue size */
 	unsigned int		evq_entries;
 	/** Hardware event ring */
@@ -191,18 +195,31 @@ typedef unsigned int (sfc_dp_rx_qdesc_npending_t)(struct sfc_dp_rxq *dp_rxq);
 /** Check Rx descriptor status */
 typedef int (sfc_dp_rx_qdesc_status_t)(struct sfc_dp_rxq *dp_rxq,
 				       uint16_t offset);
+/** Enable Rx interrupts */
+typedef int (sfc_dp_rx_intr_enable_t)(struct sfc_dp_rxq *dp_rxq);
+
+/** Disable Rx interrupts */
+typedef int (sfc_dp_rx_intr_disable_t)(struct sfc_dp_rxq *dp_rxq);
 
 /** Receive datapath definition */
 struct sfc_dp_rx {
 	struct sfc_dp				dp;
 
 	unsigned int				features;
-#define SFC_DP_RX_FEAT_SCATTER			0x1
-#define SFC_DP_RX_FEAT_MULTI_PROCESS		0x2
-#define SFC_DP_RX_FEAT_TUNNELS			0x4
-#define SFC_DP_RX_FEAT_FLOW_FLAG		0x8
-#define SFC_DP_RX_FEAT_FLOW_MARK		0x10
-#define SFC_DP_RX_FEAT_CHECKSUM			0x20
+#define SFC_DP_RX_FEAT_MULTI_PROCESS		0x1
+#define SFC_DP_RX_FEAT_FLOW_FLAG		0x2
+#define SFC_DP_RX_FEAT_FLOW_MARK		0x4
+#define SFC_DP_RX_FEAT_INTR			0x8
+	/**
+	 * Rx offload capabilities supported by the datapath on device
+	 * level only if HW/FW supports it.
+	 */
+	uint64_t				dev_offload_capa;
+	/**
+	 * Rx offload capabilities supported by the datapath per-queue
+	 * if HW/FW supports it.
+	 */
+	uint64_t				queue_offload_capa;
 	sfc_dp_rx_get_dev_info_t		*get_dev_info;
 	sfc_dp_rx_pool_ops_supported_t		*pool_ops_supported;
 	sfc_dp_rx_qsize_up_rings_t		*qsize_up_rings;
@@ -216,6 +233,8 @@ struct sfc_dp_rx {
 	sfc_dp_rx_supported_ptypes_get_t	*supported_ptypes_get;
 	sfc_dp_rx_qdesc_npending_t		*qdesc_npending;
 	sfc_dp_rx_qdesc_status_t		*qdesc_status;
+	sfc_dp_rx_intr_enable_t			*intr_enable;
+	sfc_dp_rx_intr_disable_t		*intr_disable;
 	eth_rx_burst_t				pkt_burst;
 };
 
@@ -235,6 +254,12 @@ sfc_dp_find_rx_by_caps(struct sfc_dp_list *head, unsigned int avail_caps)
 	return (p == NULL) ? NULL : container_of(p, struct sfc_dp_rx, dp);
 }
 
+static inline uint64_t
+sfc_dp_rx_offload_capa(const struct sfc_dp_rx *dp_rx)
+{
+	return dp_rx->dev_offload_capa | dp_rx->queue_offload_capa;
+}
+
 /** Get Rx datapath ops by the datapath RxQ handle */
 const struct sfc_dp_rx *sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq);