X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsfc%2Fsfc_switch.h;h=1eee5fc0b6b790fbd4c8d72e0cc37698d5672181;hb=44db08d53be366d69bb7d16bffc3e55ba2d7398a;hp=9845ac8801dac412f668e1208b1740dc63a67014;hpb=1e7fbdf0ba196004be49451dbbd85ab28a10d6a4;p=dpdk.git

diff --git a/drivers/net/sfc/sfc_switch.h b/drivers/net/sfc/sfc_switch.h
index 9845ac8801..1eee5fc0b6 100644
--- a/drivers/net/sfc/sfc_switch.h
+++ b/drivers/net/sfc/sfc_switch.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
  * Copyright(c) 2019 Solarflare Communications Inc.
  *
  * This software was jointly developed between OKTET Labs (under contract
@@ -27,20 +27,39 @@ enum sfc_mae_switch_port_type {
 	 * and thus refers to its underlying PCIe function
 	 */
 	SFC_MAE_SWITCH_PORT_INDEPENDENT = 0,
+	/**
+	 * The switch port is operated by a representor RTE ethdev
+	 * and thus refers to the represented PCIe function
+	 */
+	SFC_MAE_SWITCH_PORT_REPRESENTOR,
 };
 
 struct sfc_mae_switch_port_request {
 	enum sfc_mae_switch_port_type		type;
 	const efx_mport_sel_t			*entity_mportp;
+	const efx_mport_sel_t			*ethdev_mportp;
+	uint16_t				ethdev_port_id;
 };
 
 int sfc_mae_assign_switch_domain(struct sfc_adapter *sa,
 				 uint16_t *switch_domain_id);
 
+int sfc_mae_switch_domain_controllers(uint16_t switch_domain_id,
+				      const efx_pcie_interface_t **controllers,
+				      size_t *nb_controllers);
+
+int sfc_mae_switch_domain_map_controllers(uint16_t switch_domain_id,
+					  efx_pcie_interface_t *controllers,
+					  size_t nb_controllers);
+
 int sfc_mae_assign_switch_port(uint16_t switch_domain_id,
 			       const struct sfc_mae_switch_port_request *req,
 			       uint16_t *switch_port_id);
 
+int sfc_mae_switch_port_by_ethdev(uint16_t switch_domain_id,
+				  uint16_t ethdev_port_id,
+				  efx_mport_sel_t *mport_sel);
+
 #ifdef __cplusplus
 }
 #endif