X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Ftxgbe%2Fbase%2Ftxgbe_hw.c;h=3e7f2f9a3f237f33d6a42091f1c899e5a45d5fdc;hb=db94014c4c6084d4797b514c6d0f517cdd546076;hp=1b1d1525f75f97d4b0a33f50e4a42a1628526e8c;hpb=2102db8793c8d4ae4fcf5c608921e82c1d09dc46;p=dpdk.git diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 1b1d1525f7..3e7f2f9a3f 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -3,7 +3,10 @@ */ #include "txgbe_type.h" +#include "txgbe_mbx.h" #include "txgbe_phy.h" +#include "txgbe_dcb.h" +#include "txgbe_vf.h" #include "txgbe_eeprom.h" #include "txgbe_mng.h" #include "txgbe_hw.h" @@ -13,6 +16,7 @@ #define TXGBE_RAPTOR_RAR_ENTRIES 128 #define TXGBE_RAPTOR_MC_TBL_SIZE 128 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128 +#define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/ static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw, u32 speed, @@ -22,6 +26,164 @@ static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr); static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw, u16 *san_mac_offset); +/** + * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation + * of flow control + * @hw: pointer to hardware structure + * + * This function returns true if the device supports flow control + * autonegotiation, and false if it does not. + * + **/ +bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw) +{ + bool supported = false; + u32 speed; + bool link_up; + + DEBUGFUNC("txgbe_device_supports_autoneg_fc"); + + switch (hw->phy.media_type) { + case txgbe_media_type_fiber_qsfp: + case txgbe_media_type_fiber: + hw->mac.check_link(hw, &speed, &link_up, false); + /* if link is down, assume supported */ + if (link_up) + supported = speed == TXGBE_LINK_SPEED_1GB_FULL ? + true : false; + else + supported = true; + + break; + case txgbe_media_type_backplane: + supported = true; + break; + case txgbe_media_type_copper: + /* only some copper devices support flow control autoneg */ + switch (hw->subsystem_device_id & 0xFF) { + case TXGBE_DEV_ID_XAUI: + case TXGBE_DEV_ID_SGMII: + supported = true; + break; + default: + supported = false; + } + default: + break; + } + + if (!supported) + DEBUGOUT("Device %x does not support flow control autoneg", + hw->device_id); + return supported; +} + +/** + * txgbe_setup_fc - Set up flow control + * @hw: pointer to hardware structure + * + * Called at init time to set up flow control. + **/ +s32 txgbe_setup_fc(struct txgbe_hw *hw) +{ + s32 err = 0; + u32 reg = 0; + u16 reg_cu = 0; + u32 value = 0; + u64 reg_bp = 0; + + DEBUGFUNC("txgbe_setup_fc"); + + /* Validate the requested mode */ + if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) { + DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n"); + err = TXGBE_ERR_INVALID_LINK_SETTINGS; + goto out; + } + + /* + * 10gig parts do not have a word in the EEPROM to determine the + * default flow control setting, so we explicitly set it to full. + */ + if (hw->fc.requested_mode == txgbe_fc_default) + hw->fc.requested_mode = txgbe_fc_full; + + /* + * The possible values of fc.requested_mode are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but + * we do not support receiving pause frames). + * 3: Both Rx and Tx flow control (symmetric) are enabled. + * other: Invalid. + */ + switch (hw->fc.requested_mode) { + case txgbe_fc_none: + /* Flow control completely disabled by software override. */ + break; + case txgbe_fc_tx_pause: + /* + * Tx Flow control is enabled, and Rx Flow control is + * disabled by software override. + */ + reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM; + reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM; + break; + case txgbe_fc_rx_pause: + /* + * Rx Flow control is enabled and Tx Flow control is + * disabled by software override. Since there really + * isn't a way to advertise that we are capable of RX + * Pause ONLY, we will advertise that we support both + * symmetric and asymmetric Rx PAUSE, as such we fall + * through to the fc_full statement. Later, we will + * disable the adapter's ability to send PAUSE frames. + */ + case txgbe_fc_full: + /* Flow control (both Rx and Tx) is enabled by SW override. */ + reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM | + SR_MII_MMD_AN_ADV_PAUSE_ASM; + reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM | + SR_AN_MMD_ADV_REG1_PAUSE_ASM; + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + err = TXGBE_ERR_CONFIG; + goto out; + } + + /* + * Enable auto-negotiation between the MAC & PHY; + * the MAC will advertise clause 37 flow control. + */ + value = rd32_epcs(hw, SR_MII_MMD_AN_ADV); + value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM | + SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg; + wr32_epcs(hw, SR_MII_MMD_AN_ADV, value); + + /* + * AUTOC restart handles negotiation of 1G and 10G on backplane + * and copper. There is no need to set the PCS1GCTL register. + * + */ + if (hw->phy.media_type == txgbe_media_type_backplane) { + value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1); + value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM | + SR_AN_MMD_ADV_REG1_PAUSE_SYM)) | + reg_bp; + wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value); + } else if ((hw->phy.media_type == txgbe_media_type_copper) && + (txgbe_device_supports_autoneg_fc(hw))) { + hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT, + TXGBE_MD_DEV_AUTO_NEG, reg_cu); + } + + DEBUGOUT("Set up FC; reg = 0x%08X\n", reg); +out: + return err; +} + /** * txgbe_start_hw - Prepare hardware for Tx/Rx * @hw: pointer to hardware structure @@ -33,6 +195,7 @@ static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw, **/ s32 txgbe_start_hw(struct txgbe_hw *hw) { + s32 err; u16 device_caps; DEBUGFUNC("txgbe_start_hw"); @@ -46,6 +209,13 @@ s32 txgbe_start_hw(struct txgbe_hw *hw) /* Clear statistics registers */ hw->mac.clear_hw_cntrs(hw); + /* Setup flow control */ + err = txgbe_setup_fc(hw); + if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) { + DEBUGOUT("Flow control setup failed, returning %d\n", err); + return err; + } + /* Cache bit indicating need for crosstalk fix */ switch (hw->mac.type) { case txgbe_mac_raptor: @@ -106,6 +276,9 @@ s32 txgbe_init_hw(struct txgbe_hw *hw) DEBUGFUNC("txgbe_init_hw"); + /* Get firmware version */ + hw->phy.get_fw_version(hw, &hw->fw_version); + /* Reset the hardware */ status = hw->mac.reset_hw(hw); if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) { @@ -344,6 +517,52 @@ s32 txgbe_stop_hw(struct txgbe_hw *hw) return 0; } +/** + * txgbe_led_on - Turns on the software controllable LEDs. + * @hw: pointer to hardware structure + * @index: led number to turn on + **/ +s32 txgbe_led_on(struct txgbe_hw *hw, u32 index) +{ + u32 led_reg = rd32(hw, TXGBE_LEDCTL); + + DEBUGFUNC("txgbe_led_on"); + + if (index > 4) + return TXGBE_ERR_PARAM; + + /* To turn on the LED, set mode to ON. */ + led_reg |= TXGBE_LEDCTL_SEL(index); + led_reg |= TXGBE_LEDCTL_ORD(index); + wr32(hw, TXGBE_LEDCTL, led_reg); + txgbe_flush(hw); + + return 0; +} + +/** + * txgbe_led_off - Turns off the software controllable LEDs. + * @hw: pointer to hardware structure + * @index: led number to turn off + **/ +s32 txgbe_led_off(struct txgbe_hw *hw, u32 index) +{ + u32 led_reg = rd32(hw, TXGBE_LEDCTL); + + DEBUGFUNC("txgbe_led_off"); + + if (index > 4) + return TXGBE_ERR_PARAM; + + /* To turn off the LED, set mode to OFF. */ + led_reg &= ~(TXGBE_LEDCTL_SEL(index)); + led_reg &= ~(TXGBE_LEDCTL_ORD(index)); + wr32(hw, TXGBE_LEDCTL, led_reg); + txgbe_flush(hw); + + return 0; +} + /** * txgbe_validate_mac_addr - Validate MAC address * @mac_addr: pointer to MAC address. @@ -670,6 +889,335 @@ s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list, return 0; } +/** + * txgbe_fc_enable - Enable flow control + * @hw: pointer to hardware structure + * + * Enable flow control according to the current settings. + **/ +s32 txgbe_fc_enable(struct txgbe_hw *hw) +{ + s32 err = 0; + u32 mflcn_reg, fccfg_reg; + u32 pause_time; + u32 fcrtl, fcrth; + int i; + + DEBUGFUNC("txgbe_fc_enable"); + + /* Validate the water mark configuration */ + if (!hw->fc.pause_time) { + err = TXGBE_ERR_INVALID_LINK_SETTINGS; + goto out; + } + + /* Low water mark of zero causes XOFF floods */ + for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { + if ((hw->fc.current_mode & txgbe_fc_tx_pause) && + hw->fc.high_water[i]) { + if (!hw->fc.low_water[i] || + hw->fc.low_water[i] >= hw->fc.high_water[i]) { + DEBUGOUT("Invalid water mark configuration\n"); + err = TXGBE_ERR_INVALID_LINK_SETTINGS; + goto out; + } + } + } + + /* Negotiate the fc mode to use */ + hw->mac.fc_autoneg(hw); + + /* Disable any previous flow control settings */ + mflcn_reg = rd32(hw, TXGBE_RXFCCFG); + mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC); + + fccfg_reg = rd32(hw, TXGBE_TXFCCFG); + fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC); + + /* + * The possible values of fc.current_mode are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but + * we do not support receiving pause frames). + * 3: Both Rx and Tx flow control (symmetric) are enabled. + * other: Invalid. + */ + switch (hw->fc.current_mode) { + case txgbe_fc_none: + /* + * Flow control is disabled by software override or autoneg. + * The code below will actually disable it in the HW. + */ + break; + case txgbe_fc_rx_pause: + /* + * Rx Flow control is enabled and Tx Flow control is + * disabled by software override. Since there really + * isn't a way to advertise that we are capable of RX + * Pause ONLY, we will advertise that we support both + * symmetric and asymmetric Rx PAUSE. Later, we will + * disable the adapter's ability to send PAUSE frames. + */ + mflcn_reg |= TXGBE_RXFCCFG_FC; + break; + case txgbe_fc_tx_pause: + /* + * Tx Flow control is enabled, and Rx Flow control is + * disabled by software override. + */ + fccfg_reg |= TXGBE_TXFCCFG_FC; + break; + case txgbe_fc_full: + /* Flow control (both Rx and Tx) is enabled by SW override. */ + mflcn_reg |= TXGBE_RXFCCFG_FC; + fccfg_reg |= TXGBE_TXFCCFG_FC; + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + err = TXGBE_ERR_CONFIG; + goto out; + } + + /* Set 802.3x based flow control settings. */ + wr32(hw, TXGBE_RXFCCFG, mflcn_reg); + wr32(hw, TXGBE_TXFCCFG, fccfg_reg); + + /* Set up and enable Rx high/low water mark thresholds, enable XON. */ + for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { + if ((hw->fc.current_mode & txgbe_fc_tx_pause) && + hw->fc.high_water[i]) { + fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) | + TXGBE_FCWTRLO_XON; + fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) | + TXGBE_FCWTRHI_XOFF; + } else { + /* + * In order to prevent Tx hangs when the internal Tx + * switch is enabled we must set the high water mark + * to the Rx packet buffer size - 24KB. This allows + * the Tx switch to function even under heavy Rx + * workloads. + */ + fcrtl = 0; + fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576; + } + wr32(hw, TXGBE_FCWTRLO(i), fcrtl); + wr32(hw, TXGBE_FCWTRHI(i), fcrth); + } + + /* Configure pause time (2 TCs per register) */ + pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time); + for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++) + wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001); + + /* Configure flow control refresh threshold value */ + wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2); + +out: + return err; +} + +/** + * txgbe_negotiate_fc - Negotiate flow control + * @hw: pointer to hardware structure + * @adv_reg: flow control advertised settings + * @lp_reg: link partner's flow control settings + * @adv_sym: symmetric pause bit in advertisement + * @adv_asm: asymmetric pause bit in advertisement + * @lp_sym: symmetric pause bit in link partner advertisement + * @lp_asm: asymmetric pause bit in link partner advertisement + * + * Find the intersection between advertised settings and link partner's + * advertised settings + **/ +s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg, + u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) +{ + if ((!(adv_reg)) || (!(lp_reg))) { + DEBUGOUT("Local or link partner's advertised flow control " + "settings are NULL. Local: %x, link partner: %x\n", + adv_reg, lp_reg); + return TXGBE_ERR_FC_NOT_NEGOTIATED; + } + + if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { + /* + * Now we need to check if the user selected Rx ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->fc.requested_mode == txgbe_fc_full) { + hw->fc.current_mode = txgbe_fc_full; + DEBUGOUT("Flow Control = FULL.\n"); + } else { + hw->fc.current_mode = txgbe_fc_rx_pause; + DEBUGOUT("Flow Control=RX PAUSE frames only\n"); + } + } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && + (lp_reg & lp_sym) && (lp_reg & lp_asm)) { + hw->fc.current_mode = txgbe_fc_tx_pause; + DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); + } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && + !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { + hw->fc.current_mode = txgbe_fc_rx_pause; + DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); + } else { + hw->fc.current_mode = txgbe_fc_none; + DEBUGOUT("Flow Control = NONE.\n"); + } + return 0; +} + +/** + * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber + * @hw: pointer to hardware structure + * + * Enable flow control according on 1 gig fiber. + **/ +STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw) +{ + u32 pcs_anadv_reg, pcs_lpab_reg; + s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED; + + /* + * On multispeed fiber at 1g, bail out if + * - link is up but AN did not complete, or if + * - link is up and AN completed but timed out + */ + + pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV); + pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL); + + err = txgbe_negotiate_fc(hw, pcs_anadv_reg, + pcs_lpab_reg, + SR_MII_MMD_AN_ADV_PAUSE_SYM, + SR_MII_MMD_AN_ADV_PAUSE_ASM, + SR_MII_MMD_AN_ADV_PAUSE_SYM, + SR_MII_MMD_AN_ADV_PAUSE_ASM); + + return err; +} + +/** + * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 + * @hw: pointer to hardware structure + * + * Enable flow control according to IEEE clause 37. + **/ +STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw) +{ + u32 anlp1_reg, autoc_reg; + s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED; + + /* + * Read the 10g AN autoc and LP ability registers and resolve + * local flow control settings accordingly + */ + autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1); + anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1); + + err = txgbe_negotiate_fc(hw, autoc_reg, + anlp1_reg, + SR_AN_MMD_ADV_REG1_PAUSE_SYM, + SR_AN_MMD_ADV_REG1_PAUSE_ASM, + SR_AN_MMD_ADV_REG1_PAUSE_SYM, + SR_AN_MMD_ADV_REG1_PAUSE_ASM); + + return err; +} + +/** + * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 + * @hw: pointer to hardware structure + * + * Enable flow control according to IEEE clause 37. + **/ +STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw) +{ + u16 technology_ability_reg = 0; + u16 lp_technology_ability_reg = 0; + + hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT, + TXGBE_MD_DEV_AUTO_NEG, + &technology_ability_reg); + hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP, + TXGBE_MD_DEV_AUTO_NEG, + &lp_technology_ability_reg); + + return txgbe_negotiate_fc(hw, (u32)technology_ability_reg, + (u32)lp_technology_ability_reg, + TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE, + TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE); +} + +/** + * txgbe_fc_autoneg - Configure flow control + * @hw: pointer to hardware structure + * + * Compares our advertised flow control capabilities to those advertised by + * our link partner, and determines the proper flow control mode to use. + **/ +void txgbe_fc_autoneg(struct txgbe_hw *hw) +{ + s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED; + u32 speed; + bool link_up; + + DEBUGFUNC("txgbe_fc_autoneg"); + + /* + * AN should have completed when the cable was plugged in. + * Look for reasons to bail out. Bail out if: + * - FC autoneg is disabled, or if + * - link is not up. + */ + if (hw->fc.disable_fc_autoneg) { + DEBUGOUT("Flow control autoneg is disabled"); + goto out; + } + + hw->mac.check_link(hw, &speed, &link_up, false); + if (!link_up) { + DEBUGOUT("The link is down"); + goto out; + } + + switch (hw->phy.media_type) { + /* Autoneg flow control on fiber adapters */ + case txgbe_media_type_fiber_qsfp: + case txgbe_media_type_fiber: + if (speed == TXGBE_LINK_SPEED_1GB_FULL) + err = txgbe_fc_autoneg_fiber(hw); + break; + + /* Autoneg flow control on backplane adapters */ + case txgbe_media_type_backplane: + err = txgbe_fc_autoneg_backplane(hw); + break; + + /* Autoneg flow control on copper adapters */ + case txgbe_media_type_copper: + if (txgbe_device_supports_autoneg_fc(hw)) + err = txgbe_fc_autoneg_copper(hw); + break; + + default: + break; + } + +out: + if (err == 0) { + hw->fc.fc_was_autonegged = true; + } else { + hw->fc.fc_was_autonegged = false; + hw->fc.current_mode = hw->fc.requested_mode; + } +} + /** * txgbe_acquire_swfw_sync - Acquire SWFW semaphore * @hw: pointer to hardware structure @@ -965,6 +1513,92 @@ s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr) return 0; } +/** + * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address + * @hw: pointer to hardware struct + * @rar: receive address register index to disassociate + * @vmdq: VMDq pool index to remove from the rar + **/ +s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq) +{ + u32 mpsar_lo, mpsar_hi; + u32 rar_entries = hw->mac.num_rar_entries; + + DEBUGFUNC("txgbe_clear_vmdq"); + + /* Make sure we are using a valid rar index range */ + if (rar >= rar_entries) { + DEBUGOUT("RAR index %d is out of range.\n", rar); + return TXGBE_ERR_INVALID_ARGUMENT; + } + + wr32(hw, TXGBE_ETHADDRIDX, rar); + mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL); + mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH); + + if (TXGBE_REMOVED(hw->hw_addr)) + goto done; + + if (!mpsar_lo && !mpsar_hi) + goto done; + + if (vmdq == BIT_MASK32) { + if (mpsar_lo) { + wr32(hw, TXGBE_ETHADDRASSL, 0); + mpsar_lo = 0; + } + if (mpsar_hi) { + wr32(hw, TXGBE_ETHADDRASSH, 0); + mpsar_hi = 0; + } + } else if (vmdq < 32) { + mpsar_lo &= ~(1 << vmdq); + wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo); + } else { + mpsar_hi &= ~(1 << (vmdq - 32)); + wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi); + } + + /* was that the last pool using this rar? */ + if (mpsar_lo == 0 && mpsar_hi == 0 && + rar != 0 && rar != hw->mac.san_mac_rar_index) + hw->mac.clear_rar(hw, rar); +done: + return 0; +} + +/** + * txgbe_set_vmdq - Associate a VMDq pool index with a rx address + * @hw: pointer to hardware struct + * @rar: receive address register index to associate with a VMDq index + * @vmdq: VMDq pool index + **/ +s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq) +{ + u32 mpsar; + u32 rar_entries = hw->mac.num_rar_entries; + + DEBUGFUNC("txgbe_set_vmdq"); + + /* Make sure we are using a valid rar index range */ + if (rar >= rar_entries) { + DEBUGOUT("RAR index %d is out of range.\n", rar); + return TXGBE_ERR_INVALID_ARGUMENT; + } + + wr32(hw, TXGBE_ETHADDRIDX, rar); + if (vmdq < 32) { + mpsar = rd32(hw, TXGBE_ETHADDRASSL); + mpsar |= 1 << vmdq; + wr32(hw, TXGBE_ETHADDRASSL, mpsar); + } else { + mpsar = rd32(hw, TXGBE_ETHADDRASSH); + mpsar |= 1 << (vmdq - 32); + wr32(hw, TXGBE_ETHADDRASSH, mpsar); + } + return 0; +} + /** * txgbe_init_uta_tables - Initialize the Unicast Table Array * @hw: pointer to hardware structure @@ -982,6 +1616,214 @@ s32 txgbe_init_uta_tables(struct txgbe_hw *hw) return 0; } +/** + * txgbe_find_vlvf_slot - find the vlanid or the first empty slot + * @hw: pointer to hardware structure + * @vlan: VLAN id to write to VLAN filter + * @vlvf_bypass: true to find vlanid only, false returns first empty slot if + * vlanid not found + * + * + * return the VLVF index where this VLAN id should be placed + * + **/ +s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass) +{ + s32 regindex, first_empty_slot; + u32 bits; + + /* short cut the special case */ + if (vlan == 0) + return 0; + + /* if vlvf_bypass is set we don't want to use an empty slot, we + * will simply bypass the VLVF if there are no entries present in the + * VLVF that contain our VLAN + */ + first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0; + + /* add VLAN enable bit for comparison */ + vlan |= TXGBE_PSRVLAN_EA; + + /* Search for the vlan id in the VLVF entries. Save off the first empty + * slot found along the way. + * + * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1 + */ + for (regindex = TXGBE_NUM_POOL; --regindex;) { + wr32(hw, TXGBE_PSRVLANIDX, regindex); + bits = rd32(hw, TXGBE_PSRVLAN); + if (bits == vlan) + return regindex; + if (!first_empty_slot && !bits) + first_empty_slot = regindex; + } + + /* If we are here then we didn't find the VLAN. Return first empty + * slot we found during our search, else error. + */ + if (!first_empty_slot) + DEBUGOUT("No space in VLVF.\n"); + + return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE; +} + +/** + * txgbe_set_vfta - Set VLAN filter table + * @hw: pointer to hardware structure + * @vlan: VLAN id to write to VLAN filter + * @vind: VMDq output index that maps queue to VLAN id in VLVFB + * @vlan_on: boolean flag to turn on/off VLAN + * @vlvf_bypass: boolean flag indicating updating default pool is okay + * + * Turn on/off specified VLAN in the VLAN filter table. + **/ +s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind, + bool vlan_on, bool vlvf_bypass) +{ + u32 regidx, vfta_delta, vfta; + s32 err; + + DEBUGFUNC("txgbe_set_vfta"); + + if (vlan > 4095 || vind > 63) + return TXGBE_ERR_PARAM; + + /* + * this is a 2 part operation - first the VFTA, then the + * VLVF and VLVFB if VT Mode is set + * We don't write the VFTA until we know the VLVF part succeeded. + */ + + /* Part 1 + * The VFTA is a bitstring made up of 128 32-bit registers + * that enable the particular VLAN id, much like the MTA: + * bits[11-5]: which register + * bits[4-0]: which bit in the register + */ + regidx = vlan / 32; + vfta_delta = 1 << (vlan % 32); + vfta = rd32(hw, TXGBE_VLANTBL(regidx)); + + /* + * vfta_delta represents the difference between the current value + * of vfta and the value we want in the register. Since the diff + * is an XOR mask we can just update the vfta using an XOR + */ + vfta_delta &= vlan_on ? ~vfta : vfta; + vfta ^= vfta_delta; + + /* Part 2 + * Call txgbe_set_vlvf to set VLVFB and VLVF + */ + err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta, + vfta, vlvf_bypass); + if (err != 0) { + if (vlvf_bypass) + goto vfta_update; + return err; + } + +vfta_update: + /* Update VFTA now that we are ready for traffic */ + if (vfta_delta) + wr32(hw, TXGBE_VLANTBL(regidx), vfta); + + return 0; +} + +/** + * txgbe_set_vlvf - Set VLAN Pool Filter + * @hw: pointer to hardware structure + * @vlan: VLAN id to write to VLAN filter + * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM + * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN + * @vfta_delta: pointer to the difference between the current value + * of PSRVLANPLM and the desired value + * @vfta: the desired value of the VFTA + * @vlvf_bypass: boolean flag indicating updating default pool is okay + * + * Turn on/off specified bit in VLVF table. + **/ +s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind, + bool vlan_on, u32 *vfta_delta, u32 vfta, + bool vlvf_bypass) +{ + u32 bits; + u32 portctl; + s32 vlvf_index; + + DEBUGFUNC("txgbe_set_vlvf"); + + if (vlan > 4095 || vind > 63) + return TXGBE_ERR_PARAM; + + /* If VT Mode is set + * Either vlan_on + * make sure the vlan is in PSRVLAN + * set the vind bit in the matching PSRVLANPLM + * Or !vlan_on + * clear the pool bit and possibly the vind + */ + portctl = rd32(hw, TXGBE_PORTCTL); + if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK)) + return 0; + + vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); + if (vlvf_index < 0) + return vlvf_index; + + wr32(hw, TXGBE_PSRVLANIDX, vlvf_index); + bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32)); + + /* set the pool bit */ + bits |= 1 << (vind % 32); + if (vlan_on) + goto vlvf_update; + + /* clear the pool bit */ + bits ^= 1 << (vind % 32); + + if (!bits && + !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) { + /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise + * we run the risk of stray packets leaking into + * the PF via the default pool + */ + if (*vfta_delta) + wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta); + + /* disable VLVF and clear remaining bit from pool */ + wr32(hw, TXGBE_PSRVLAN, 0); + wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0); + + return 0; + } + + /* If there are still bits set in the PSRVLANPLM registers + * for the VLAN ID indicated we need to see if the + * caller is requesting that we clear the PSRVLANPLM entry bit. + * If the caller has requested that we clear the PSRVLANPLM + * entry bit but there are still pools/VFs using this VLAN + * ID entry then ignore the request. We're not worried + * about the case where we're turning the PSRVLANPLM VLAN ID + * entry bit on, only when requested to turn it off as + * there may be multiple pools and/or VFs using the + * VLAN ID entry. In that case we cannot clear the + * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also + * been cleared. This will be indicated by "bits" being + * zero. + */ + *vfta_delta = 0; + +vlvf_update: + /* record pool change and enable VLAN ID if not already enabled */ + wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits); + wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan); + + return 0; +} + /** * txgbe_clear_vfta - Clear VLAN filter table * @hw: pointer to hardware structure @@ -1172,6 +2014,49 @@ wwn_prefix_err: return 0; } +/** + * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing + * @hw: pointer to hardware structure + * @enable: enable or disable switch for MAC anti-spoofing + * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing + * + **/ +void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf) +{ + int vf_target_reg = vf >> 3; + int vf_target_shift = vf % 8; + u32 pfvfspoof; + + pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg)); + if (enable) + pfvfspoof |= (1 << vf_target_shift); + else + pfvfspoof &= ~(1 << vf_target_shift); + wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof); +} + +/** + * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing + * @hw: pointer to hardware structure + * @enable: enable or disable switch for Ethertype anti-spoofing + * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing + * + **/ +void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw, + bool enable, int vf) +{ + int vf_target_reg = vf >> 3; + int vf_target_shift = vf % 8; + u32 pfvfspoof; + + pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg)); + if (enable) + pfvfspoof |= (1 << vf_target_shift); + else + pfvfspoof &= ~(1 << vf_target_shift); + wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof); +} + /** * txgbe_get_device_caps - Get additional device capabilities * @hw: pointer to hardware structure @@ -1189,6 +2074,68 @@ s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps) return 0; } +/** + * txgbe_set_pba - Initialize Rx packet buffer + * @hw: pointer to hardware structure + * @num_pb: number of packet buffers to allocate + * @headroom: reserve n KB of headroom + * @strategy: packet buffer allocation strategy + **/ +void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom, + int strategy) +{ + u32 pbsize = hw->mac.rx_pb_size; + int i = 0; + u32 rxpktsize, txpktsize, txpbthresh; + + UNREFERENCED_PARAMETER(hw); + + /* Reserve headroom */ + pbsize -= headroom; + + if (!num_pb) + num_pb = 1; + + /* Divide remaining packet buffer space amongst the number of packet + * buffers requested using supplied strategy. + */ + switch (strategy) { + case PBA_STRATEGY_WEIGHTED: + /* txgbe_dcb_pba_80_48 strategy weight first half of packet + * buffer with 5/8 of the packet buffer space. + */ + rxpktsize = (pbsize * 5) / (num_pb * 4); + pbsize -= rxpktsize * (num_pb / 2); + rxpktsize <<= 10; + for (; i < (num_pb / 2); i++) + wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize); + /* fall through - configure remaining packet buffers */ + case PBA_STRATEGY_EQUAL: + rxpktsize = (pbsize / (num_pb - i)); + rxpktsize <<= 10; + for (; i < num_pb; i++) + wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize); + break; + default: + break; + } + + /* Only support an equally distributed Tx packet buffer strategy. */ + txpktsize = TXGBE_PBTXSIZE_MAX / num_pb; + txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX; + for (i = 0; i < num_pb; i++) { + wr32(hw, TXGBE_PBTXSIZE(i), txpktsize); + wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh); + } + + /* Clear unused TCs, if any, to zero buffer size*/ + for (; i < TXGBE_MAX_UP; i++) { + wr32(hw, TXGBE_PBRXSIZE(i), 0); + wr32(hw, TXGBE_PBTXSIZE(i), 0); + wr32(hw, TXGBE_PBTXDMATH(i), 0); + } +} + /** * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo * @hw: pointer to the hardware structure @@ -1501,6 +2448,9 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw) case txgbe_mac_raptor: status = txgbe_init_ops_pf(hw); break; + case txgbe_mac_raptor_vf: + status = txgbe_init_ops_vf(hw); + break; default: status = TXGBE_ERR_DEVICE_NOT_SUPPORTED; break; @@ -1531,26 +2481,12 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) } switch (hw->device_id) { - case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4: - hw->phy.media_type = txgbe_media_type_backplane; - hw->mac.type = txgbe_mac_raptor; - break; - case TXGBE_DEV_ID_RAPTOR_XAUI: - case TXGBE_DEV_ID_RAPTOR_SGMII: - hw->phy.media_type = txgbe_media_type_copper; + case TXGBE_DEV_ID_SP1000: + case TXGBE_DEV_ID_WX1820: hw->mac.type = txgbe_mac_raptor; break; - case TXGBE_DEV_ID_RAPTOR_SFP: - case TXGBE_DEV_ID_WX1820_SFP: - hw->phy.media_type = txgbe_media_type_fiber; - hw->mac.type = txgbe_mac_raptor; - break; - case TXGBE_DEV_ID_RAPTOR_QSFP: - hw->phy.media_type = txgbe_media_type_fiber_qsfp; - hw->mac.type = txgbe_mac_raptor; - break; - case TXGBE_DEV_ID_RAPTOR_VF: - case TXGBE_DEV_ID_RAPTOR_VF_HV: + case TXGBE_DEV_ID_SP1000_VF: + case TXGBE_DEV_ID_WX1820_VF: hw->phy.media_type = txgbe_media_type_virtual; hw->mac.type = txgbe_mac_raptor_vf; break; @@ -1560,8 +2496,8 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) break; } - DEBUGOUT("found mac: %d media: %d, returns: %d\n", - hw->mac.type, hw->phy.media_type, err); + DEBUGOUT("found mac: %d, returns: %d\n", + hw->mac.type, err); return err; } @@ -1592,13 +2528,9 @@ void txgbe_init_mac_link_ops(struct txgbe_hw *hw) mac->setup_link = txgbe_setup_mac_link_multispeed_fiber; mac->setup_mac_link = txgbe_setup_mac_link; mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed; - } else if ((hw->phy.media_type == txgbe_media_type_backplane) && - (hw->phy.smart_speed == txgbe_smart_speed_auto || - hw->phy.smart_speed == txgbe_smart_speed_on) && - !txgbe_verify_lesm_fw_enabled_raptor(hw)) { - mac->setup_link = txgbe_setup_mac_link_smartspeed; } else { mac->setup_link = txgbe_setup_mac_link; + mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed; } } @@ -1619,7 +2551,7 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw) DEBUGFUNC("txgbe_init_phy_raptor"); - if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) { + if ((hw->device_id & 0xFF) == TXGBE_DEV_ID_QSFP) { /* Store flag indicating I2C bus access control unit. */ hw->phy.qsfp_shared_i2c_bus = TRUE; @@ -1642,6 +2574,11 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw) txgbe_get_copper_link_capabilities; } + if (phy->media_type == txgbe_media_type_backplane) { + mac->kr_handle = txgbe_kr_handle; + mac->bp_down_event = txgbe_bp_down_event; + } + /* Set necessary function pointers based on PHY type */ switch (hw->phy.type) { case txgbe_phy_tn: @@ -1688,6 +2625,82 @@ s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw) return err; } +/** + * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read + * @hw: pointer to hardware structure + * @locked: Return the if we locked for this read. + * @value: Value we read from AUTOC + * + * For this part we need to wrap read-modify-writes with a possible + * FW/SW lock. It is assumed this lock will be freed with the next + * prot_autoc_write_raptor(). + */ +s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value) +{ + s32 err; + bool lock_state = false; + + /* If LESM is on then we need to hold the SW/FW semaphore. */ + if (txgbe_verify_lesm_fw_enabled_raptor(hw)) { + err = hw->mac.acquire_swfw_sync(hw, + TXGBE_MNGSEM_SWPHY); + if (err != 0) + return TXGBE_ERR_SWFW_SYNC; + + lock_state = true; + } + + if (locked) + *locked = lock_state; + + *value = txgbe_autoc_read(hw); + return 0; +} + +/** + * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write + * @hw: pointer to hardware structure + * @autoc: value to write to AUTOC + * @locked: bool to indicate whether the SW/FW lock was already taken by + * previous prot_autoc_read_raptor. + * + * This part may need to hold the SW/FW lock around all writes to + * AUTOC. Likewise after a write we need to do a pipeline reset. + */ +s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc) +{ + int err = 0; + + /* Blocked by MNG FW so bail */ + if (txgbe_check_reset_blocked(hw)) + goto out; + + /* We only need to get the lock if: + * - We didn't do it already (in the read part of a read-modify-write) + * - LESM is enabled. + */ + if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) { + err = hw->mac.acquire_swfw_sync(hw, + TXGBE_MNGSEM_SWPHY); + if (err != 0) + return TXGBE_ERR_SWFW_SYNC; + + locked = true; + } + + txgbe_autoc_write(hw, autoc); + err = txgbe_reset_pipeline_raptor(hw); + +out: + /* Free the SW/FW semaphore as we either grabbed it here or + * already had it when this function was called. + */ + if (locked) + hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY); + + return err; +} + /** * txgbe_init_ops_pf - Inits func ptrs and MAC type * @hw: pointer to hardware structure @@ -1701,6 +2714,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) struct txgbe_mac_info *mac = &hw->mac; struct txgbe_phy_info *phy = &hw->phy; struct txgbe_rom_info *rom = &hw->rom; + struct txgbe_mbx_info *mbx = &hw->mbx; DEBUGFUNC("txgbe_init_ops_pf"); @@ -1717,10 +2731,15 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) phy->write_reg_mdi = txgbe_write_phy_reg_mdi; phy->setup_link = txgbe_setup_phy_link; phy->setup_link_speed = txgbe_setup_phy_link_speed; + phy->get_fw_version = txgbe_get_phy_fw_version; phy->read_i2c_byte = txgbe_read_i2c_byte; phy->write_i2c_byte = txgbe_write_i2c_byte; + phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472; phy->read_i2c_eeprom = txgbe_read_i2c_eeprom; phy->write_i2c_eeprom = txgbe_write_i2c_eeprom; + phy->identify_sfp = txgbe_identify_module; + phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked; + phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked; phy->reset = txgbe_reset_phy; /* MAC */ @@ -1733,6 +2752,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) mac->acquire_swfw_sync = txgbe_acquire_swfw_sync; mac->release_swfw_sync = txgbe_release_swfw_sync; mac->reset_hw = txgbe_reset_hw; + mac->update_mc_addr_list = txgbe_update_mc_addr_list; mac->disable_sec_rx_path = txgbe_disable_sec_rx_path; mac->enable_sec_rx_path = txgbe_enable_sec_rx_path; @@ -1744,24 +2764,47 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) mac->get_wwn_prefix = txgbe_get_wwn_prefix; mac->autoc_read = txgbe_autoc_read; mac->autoc_write = txgbe_autoc_write; + mac->prot_autoc_read = txgbe_prot_autoc_read_raptor; + mac->prot_autoc_write = txgbe_prot_autoc_write_raptor; + /* RAR, Multicast, VLAN */ mac->set_rar = txgbe_set_rar; mac->clear_rar = txgbe_clear_rar; mac->init_rx_addrs = txgbe_init_rx_addrs; mac->enable_rx = txgbe_enable_rx; mac->disable_rx = txgbe_disable_rx; + mac->set_vmdq = txgbe_set_vmdq; + mac->clear_vmdq = txgbe_clear_vmdq; + mac->set_vfta = txgbe_set_vfta; + mac->set_vlvf = txgbe_set_vlvf; mac->clear_vfta = txgbe_clear_vfta; mac->init_uta_tables = txgbe_init_uta_tables; mac->setup_sfp = txgbe_setup_sfp_modules; + mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing; + mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing; + + /* Flow Control */ + mac->fc_enable = txgbe_fc_enable; + mac->setup_fc = txgbe_setup_fc; + mac->fc_autoneg = txgbe_fc_autoneg; + /* Link */ mac->get_link_capabilities = txgbe_get_link_capabilities_raptor; mac->check_link = txgbe_check_mac_link; + mac->setup_pba = txgbe_set_pba; /* Manageability interface */ mac->set_fw_drv_ver = txgbe_hic_set_drv_ver; mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data; mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh; + mbx->init_params = txgbe_init_mbx_params_pf; + mbx->read = txgbe_read_mbx_pf; + mbx->write = txgbe_write_mbx_pf; + mbx->check_for_msg = txgbe_check_for_msg_pf; + mbx->check_for_ack = txgbe_check_for_ack_pf; + mbx->check_for_rst = txgbe_check_for_rst_pf; + /* EEPROM */ rom->init_params = txgbe_init_eeprom_params; rom->read16 = txgbe_ee_read16; @@ -1779,6 +2822,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE; mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE; mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES; + mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE; mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES; mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES; @@ -1907,6 +2951,9 @@ u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw) DEBUGFUNC("txgbe_get_media_type_raptor"); + if (hw->phy.ffe_set) + txgbe_bp_mode_set(hw); + /* Detect if there is a copper PHY attached. */ switch (hw->phy.type) { case txgbe_phy_cu_unknown: @@ -1917,22 +2964,29 @@ u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw) break; } - switch (hw->device_id) { - case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4: + switch (hw->subsystem_device_id & 0xFF) { + case TXGBE_DEV_ID_KR_KX_KX4: + case TXGBE_DEV_ID_MAC_SGMII: + case TXGBE_DEV_ID_MAC_XAUI: /* Default device ID is mezzanine card KX/KX4 */ media_type = txgbe_media_type_backplane; break; - case TXGBE_DEV_ID_RAPTOR_SFP: - case TXGBE_DEV_ID_WX1820_SFP: + case TXGBE_DEV_ID_SFP: media_type = txgbe_media_type_fiber; break; - case TXGBE_DEV_ID_RAPTOR_QSFP: + case TXGBE_DEV_ID_QSFP: media_type = txgbe_media_type_fiber_qsfp; break; - case TXGBE_DEV_ID_RAPTOR_XAUI: - case TXGBE_DEV_ID_RAPTOR_SGMII: + case TXGBE_DEV_ID_XAUI: + case TXGBE_DEV_ID_SGMII: media_type = txgbe_media_type_copper; break; + case TXGBE_DEV_ID_SFI_XAUI: + if (hw->bus.lan_id == 0) + media_type = txgbe_media_type_fiber; + else + media_type = txgbe_media_type_copper; + break; default: media_type = txgbe_media_type_unknown; break; @@ -2212,13 +3266,11 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw, u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK; u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK; u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK; - u64 current_autoc = autoc; u64 orig_autoc = 0; - u32 links_reg; - u32 i; u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN; DEBUGFUNC("txgbe_setup_mac_link"); + UNREFERENCED_PARAMETER(autoneg_wait_to_complete); /* Check to see if speed passed in is supported. */ status = hw->mac.get_link_capabilities(hw, @@ -2249,8 +3301,7 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw, if (speed & TXGBE_LINK_SPEED_10GB_FULL) { if (orig_autoc & TXGBE_AUTOC_KX4_SUPP) autoc |= TXGBE_AUTOC_KX4_SUPP; - if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) && - !hw->phy.smart_speed_active) + if (orig_autoc & TXGBE_AUTOC_KR_SUPP) autoc |= TXGBE_AUTOC_KR_SUPP; } if (speed & TXGBE_LINK_SPEED_1GB_FULL) @@ -2277,35 +3328,14 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw, } } - if (autoc == current_autoc) - return status; - autoc &= ~TXGBE_AUTOC_SPEED_MASK; autoc |= TXGBE_AUTOC_SPEED(speed); + autoc &= ~TXGBE_AUTOC_AUTONEG; autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0); /* Restart link */ hw->mac.autoc_write(hw, autoc); - /* Only poll for autoneg to complete if specified to do so */ - if (autoneg_wait_to_complete) { - if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR || - link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || - link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { - links_reg = 0; /*Just in case Autoneg time=0*/ - for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) { - links_reg = rd32(hw, TXGBE_PORTSTAT); - if (links_reg & TXGBE_PORTSTAT_UP) - break; - msec_delay(100); - } - if (!(links_reg & TXGBE_PORTSTAT_UP)) { - status = TXGBE_ERR_AUTONEG_NOT_COMPLETE; - DEBUGOUT("Autoneg did not complete.\n"); - } - } - } - /* Add delay to filter out noises during initial link setup */ msec_delay(50); @@ -2418,6 +3448,7 @@ txgbe_reset_misc(struct txgbe_hw *hw) /* enable mac transmitter */ wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE); + hw->mac.autoc = hw->mac.orig_autoc; for (i = 0; i < 4; i++) wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0); } @@ -2511,12 +3542,19 @@ mac_reset_top: */ if (!hw->mac.orig_link_settings_stored) { hw->mac.orig_autoc = hw->mac.autoc_read(hw); - hw->mac.autoc_write(hw, hw->mac.orig_autoc); hw->mac.orig_link_settings_stored = true; } else { hw->mac.orig_autoc = autoc; } + if (hw->phy.ffe_set) { + /* Make sure phy power is up */ + msec_delay(50); + + /* A temporary solution to set phy */ + txgbe_set_phy_temp(hw); + } + /* Store the permanent mac address */ hw->mac.get_mac_addr(hw, hw->mac.perm_addr); @@ -2554,6 +3592,93 @@ mac_reset_top: return status; } +/** + * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete + * @hw: pointer to hardware structure + * @fdircmd: current value of FDIRCMD register + */ +static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd) +{ + int i; + + for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) { + *fdircmd = rd32(hw, TXGBE_FDIRPICMD); + if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK)) + return 0; + usec_delay(10); + } + + return TXGBE_ERR_FDIR_CMD_INCOMPLETE; +} + +/** + * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables. + * @hw: pointer to hardware structure + **/ +s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw) +{ + s32 err; + int i; + u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL); + u32 fdircmd; + fdirctrl &= ~TXGBE_FDIRCTL_INITDONE; + + DEBUGFUNC("txgbe_reinit_fdir_tables"); + + /* + * Before starting reinitialization process, + * FDIRPICMD.OP must be zero. + */ + err = txgbe_fdir_check_cmd_complete(hw, &fdircmd); + if (err) { + DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); + return err; + } + + wr32(hw, TXGBE_FDIRFREE, 0); + txgbe_flush(hw); + /* + * adapters flow director init flow cannot be restarted, + * Workaround silicon errata by performing the following steps + * before re-writing the FDIRCTL control register with the same value. + * - write 1 to bit 8 of FDIRPICMD register & + * - write 0 to bit 8 of FDIRPICMD register + */ + wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR); + txgbe_flush(hw); + wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0); + txgbe_flush(hw); + /* + * Clear FDIR Hash register to clear any leftover hashes + * waiting to be programmed. + */ + wr32(hw, TXGBE_FDIRPIHASH, 0x00); + txgbe_flush(hw); + + wr32(hw, TXGBE_FDIRCTL, fdirctrl); + txgbe_flush(hw); + + /* Poll init-done after we write FDIRCTL register */ + for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) { + if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE)) + break; + msec_delay(1); + } + if (i >= TXGBE_FDIR_INIT_DONE_POLL) { + DEBUGOUT("Flow Director Signature poll time exceeded!\n"); + return TXGBE_ERR_FDIR_REINIT_FAILED; + } + + /* Clear FDIR statistics registers (read to clear) */ + rd32(hw, TXGBE_FDIRUSED); + rd32(hw, TXGBE_FDIRFAIL); + rd32(hw, TXGBE_FDIRMATCH); + rd32(hw, TXGBE_FDIRMISS); + rd32(hw, TXGBE_FDIRLEN); + + return 0; +} + /** * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx * @hw: pointer to hardware structure