X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Ftxgbe%2Fbase%2Ftxgbe_type.h;h=b69e7b85baf75db341f45201150210a1a9f2b35a;hb=db94014c4c6084d4797b514c6d0f517cdd546076;hp=539d1fb4d4c4a19942efdb47f48370117277d3ce;hpb=2102db8793c8d4ae4fcf5c608921e82c1d09dc46;p=dpdk.git diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 539d1fb4d4..b69e7b85ba 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -5,16 +5,29 @@ #ifndef _TXGBE_TYPE_H_ #define _TXGBE_TYPE_H_ +#define TXGBE_DCB_TC_MAX TXGBE_MAX_UP +#define TXGBE_DCB_UP_MAX TXGBE_MAX_UP +#define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ +#define TXGBE_RX_HDR_SIZE 256 +#define TXGBE_RX_BUF_SIZE 2048 + #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */ #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */ #define TXGBE_NUM_POOL (64) +#define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ +#define TXGBE_MAX_FTQF_FILTERS 128 +#define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ #define TXGBE_MAX_UP 8 #define TXGBE_MAX_QP (128) #define TXGBE_MAX_UTA 128 +#define TXGBE_FDIR_INIT_DONE_POLL 10 +#define TXGBE_FDIRCMD_CMD_POLL 10 +#define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ + #define TXGBE_ALIGN 128 /* as intel did */ #include "txgbe_status.h" @@ -31,6 +44,14 @@ struct txgbe_thermal_sensor_data { struct txgbe_thermal_diode_data sensor[1]; }; +/* Packet buffer allocation strategies */ +enum { + PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ +#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL + PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ +#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED +}; + /* Physical layer type */ #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001 @@ -51,7 +72,68 @@ struct txgbe_thermal_sensor_data { #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 +/* Software ATR hash keys */ +#define TXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 +#define TXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 + +/* Software ATR input stream values and masks */ #define TXGBE_ATR_HASH_MASK 0x7fff +#define TXGBE_ATR_L3TYPE_MASK 0x4 +#define TXGBE_ATR_L3TYPE_IPV4 0x0 +#define TXGBE_ATR_L3TYPE_IPV6 0x4 +#define TXGBE_ATR_L4TYPE_MASK 0x3 +#define TXGBE_ATR_L4TYPE_UDP 0x1 +#define TXGBE_ATR_L4TYPE_TCP 0x2 +#define TXGBE_ATR_L4TYPE_SCTP 0x3 +#define TXGBE_ATR_TUNNEL_MASK 0x10 +#define TXGBE_ATR_TUNNEL_ANY 0x10 +enum txgbe_atr_flow_type { + TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, + TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, + TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, + TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, + TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, + TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, + TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, + TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, + TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, + TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, + TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, + TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, + TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, + TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, + TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, + TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, +}; + +/* Flow Director ATR input struct. */ +struct txgbe_atr_input { + /* + * Byte layout in order, all values with MSB first: + * + * vm_pool - 1 byte + * flow_type - 1 byte + * vlan_id - 2 bytes + * src_ip - 16 bytes + * inner_mac - 6 bytes + * cloud_mode - 2 bytes + * tni_vni - 4 bytes + * dst_ip - 16 bytes + * src_port - 2 bytes + * dst_port - 2 bytes + * flex_bytes - 2 bytes + * bkt_hash - 2 bytes + */ + u8 vm_pool; + u8 flow_type; + __be16 pkt_type; + __be32 dst_ip[4]; + __be32 src_ip[4]; + __be16 src_port; + __be16 dst_port; + __be16 flex_bytes; + __be16 bkt_hash; +}; enum txgbe_eeprom_type { txgbe_eeprom_unknown = 0, @@ -140,6 +222,14 @@ enum txgbe_media_type { txgbe_media_type_virtual }; +/* Flow Control Settings */ +enum txgbe_fc_mode { + txgbe_fc_none = 0, + txgbe_fc_rx_pause, + txgbe_fc_tx_pause, + txgbe_fc_full, + txgbe_fc_default +}; /* Smart Speed Settings */ #define TXGBE_SMARTSPEED_MAX_RETRIES 3 @@ -209,6 +299,19 @@ struct txgbe_bus_info { u16 instance_id; }; +/* Flow control parameters */ +struct txgbe_fc_info { + u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */ + u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */ + u16 pause_time; /* Flow Control Pause timer */ + bool send_xon; /* Flow control send XON */ + bool strict_ieee; /* Strict IEEE mode */ + bool disable_fc_autoneg; /* Do not autonegotiate FC */ + bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ + enum txgbe_fc_mode current_mode; /* FC mode in effect */ + enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */ +}; + /* Statistics counters collected by the MAC */ /* PB[] RxTx */ struct txgbe_pb_stats { @@ -250,6 +353,7 @@ struct txgbe_hw_stats { u64 rx_management_packets; u64 tx_management_packets; u64 rx_management_dropped; + u64 rx_dma_drop; u64 rx_drop_packets; /* Basic Error */ @@ -496,6 +600,9 @@ struct txgbe_mac_info { s32 (*dmac_config)(struct txgbe_hw *hw); s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee); + s32 (*kr_handle)(struct txgbe_hw *hw); + void (*bp_down_event)(struct txgbe_hw *hw); + enum txgbe_mac_type type; u8 addr[ETH_ADDR_LEN]; u8 perm_addr[ETH_ADDR_LEN]; @@ -510,12 +617,13 @@ struct txgbe_mac_info { u32 mcft_size; u32 vft_size; u32 num_rar_entries; + u32 rx_pb_size; u32 max_tx_queues; u32 max_rx_queues; - + u64 autoc; + u64 orig_autoc; /* cached value of AUTOC */ u8 san_mac_rar_index; bool get_link_status; - u64 orig_autoc; /* cached value of AUTOC */ bool orig_link_settings_stored; bool autotry_restart; u8 flags; @@ -543,6 +651,7 @@ struct txgbe_phy_info { s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed, bool autoneg_wait_to_complete); s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up); + s32 (*get_fw_version)(struct txgbe_hw *hw, u32 *fw_version); s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data); s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, @@ -578,6 +687,42 @@ struct txgbe_phy_info { bool qsfp_shared_i2c_bus; u32 nw_mng_if_sel; u32 link_mode; + + /* Some features need tri-state capability */ + u16 ffe_set; + u16 ffe_main; + u16 ffe_pre; + u16 ffe_post; +}; + +#define TXGBE_DEVARG_BP_AUTO "auto_neg" +#define TXGBE_DEVARG_KR_POLL "poll" +#define TXGBE_DEVARG_KR_PRESENT "present" +#define TXGBE_DEVARG_KX_SGMII "sgmii" +#define TXGBE_DEVARG_FFE_SET "ffe_set" +#define TXGBE_DEVARG_FFE_MAIN "ffe_main" +#define TXGBE_DEVARG_FFE_PRE "ffe_pre" +#define TXGBE_DEVARG_FFE_POST "ffe_post" + +static const char * const txgbe_valid_arguments[] = { + TXGBE_DEVARG_BP_AUTO, + TXGBE_DEVARG_KR_POLL, + TXGBE_DEVARG_KR_PRESENT, + TXGBE_DEVARG_KX_SGMII, + TXGBE_DEVARG_FFE_SET, + TXGBE_DEVARG_FFE_MAIN, + TXGBE_DEVARG_FFE_PRE, + TXGBE_DEVARG_FFE_POST, + NULL +}; + +struct txgbe_mbx_stats { + u32 msgs_tx; + u32 msgs_rx; + + u32 acks; + u32 reqs; + u32 rsts; }; struct txgbe_mbx_info { @@ -591,6 +736,12 @@ struct txgbe_mbx_info { s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id); s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id); s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id); + + struct txgbe_mbx_stats stats; + u32 timeout; + u32 usec_delay; + u32 v2p_mailbox; + u16 size; }; enum txgbe_isb_idx { @@ -601,11 +752,19 @@ enum txgbe_isb_idx { TXGBE_ISB_MAX }; +struct txgbe_devargs { + u16 auto_neg; + u16 poll; + u16 present; + u16 sgmii; +}; + struct txgbe_hw { void IOMEM *hw_addr; void *back; struct txgbe_mac_info mac; struct txgbe_addr_filter_info addr_ctrl; + struct txgbe_fc_info fc; struct txgbe_phy_info phy; struct txgbe_link_info link; struct txgbe_rom_info rom; @@ -616,14 +775,20 @@ struct txgbe_hw { u16 vendor_id; u16 subsystem_device_id; u16 subsystem_vendor_id; + u8 revision_id; bool adapter_stopped; + int api_version; bool allow_unsupported_sfp; bool need_crosstalk_fix; + struct txgbe_devargs devarg; uint64_t isb_dma; void IOMEM *isb_mem; u16 nb_rx_queues; u16 nb_tx_queues; + + u32 fw_version; + u32 mode; enum txgbe_link_status { TXGBE_LINK_STATUS_NONE = 0, TXGBE_LINK_STATUS_KX, @@ -638,6 +803,7 @@ struct txgbe_hw { u32 q_rx_regs[128 * 4]; u32 q_tx_regs[128 * 4]; bool offset_loaded; + bool rx_loaded; struct { u64 rx_qp_packets; u64 tx_qp_packets; @@ -647,6 +813,13 @@ struct txgbe_hw { } qp_last[TXGBE_MAX_QP]; }; +struct txgbe_backplane_ability { + u32 next_page; /* Next Page (bit0) */ + u32 link_ability; /* Link Ability (bit[7:0]) */ + u32 fec_ability; /* FEC Request (bit1), FEC Enable (bit0) */ + u32 current_link_mode; /* current link mode for local device */ +}; + #include "txgbe_regs.h" #include "txgbe_dummy.h"