X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Ftxgbe%2Fbase%2Ftxgbe_type.h;h=d95467f9f89cae14a26cd76781fe3282a011b339;hb=ed2ffccdc1c862a24361f67dcf470428be142418;hp=633692cd7b3fd4563a622a9189741bd8c9c585a8;hpb=ea230dda16ad65574b94408f43a92a9263cb7f37;p=dpdk.git

diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 633692cd7b..d95467f9f8 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-2020
+ * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
  */
 
 #ifndef _TXGBE_TYPE_H_
@@ -11,6 +12,9 @@
 #define TXGBE_LINK_UP_TIME	90 /* 9.0 Seconds */
 #define TXGBE_AUTO_NEG_TIME	45 /* 4.5 Seconds */
 
+#define TXGBE_RX_HDR_SIZE	256
+#define TXGBE_RX_BUF_SIZE	2048
+
 #define TXGBE_FRAME_SIZE_MAX	(9728) /* Maximum frame size, +FCS */
 #define TXGBE_FRAME_SIZE_DFT	(1518) /* Default frame size, +FCS */
 #define TXGBE_NUM_POOL		(64)
@@ -22,6 +26,8 @@
 #define TXGBE_MAX_UTA		128
 
 #define TXGBE_FDIR_INIT_DONE_POLL		10
+#define TXGBE_FDIRCMD_CMD_POLL			10
+#define TXGBE_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
 
 #define TXGBE_ALIGN		128 /* as intel did */
 
@@ -71,7 +77,35 @@ enum {
 #define TXGBE_ATR_BUCKET_HASH_KEY		0x3DAD14E2
 #define TXGBE_ATR_SIGNATURE_HASH_KEY		0x174D3614
 
+/* Software ATR input stream values and masks */
 #define TXGBE_ATR_HASH_MASK			0x7fff
+#define TXGBE_ATR_L3TYPE_MASK			0x4
+#define TXGBE_ATR_L3TYPE_IPV4			0x0
+#define TXGBE_ATR_L3TYPE_IPV6			0x4
+#define TXGBE_ATR_L4TYPE_MASK			0x3
+#define TXGBE_ATR_L4TYPE_UDP			0x1
+#define TXGBE_ATR_L4TYPE_TCP			0x2
+#define TXGBE_ATR_L4TYPE_SCTP			0x3
+#define TXGBE_ATR_TUNNEL_MASK			0x10
+#define TXGBE_ATR_TUNNEL_ANY			0x10
+enum txgbe_atr_flow_type {
+	TXGBE_ATR_FLOW_TYPE_IPV4		= 0x0,
+	TXGBE_ATR_FLOW_TYPE_UDPV4		= 0x1,
+	TXGBE_ATR_FLOW_TYPE_TCPV4		= 0x2,
+	TXGBE_ATR_FLOW_TYPE_SCTPV4		= 0x3,
+	TXGBE_ATR_FLOW_TYPE_IPV6		= 0x4,
+	TXGBE_ATR_FLOW_TYPE_UDPV6		= 0x5,
+	TXGBE_ATR_FLOW_TYPE_TCPV6		= 0x6,
+	TXGBE_ATR_FLOW_TYPE_SCTPV6		= 0x7,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4	= 0x10,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4	= 0x11,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4	= 0x12,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4	= 0x13,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6	= 0x14,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6	= 0x15,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6	= 0x16,
+	TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6	= 0x17,
+};
 
 /* Flow Director ATR input struct. */
 struct txgbe_atr_input {
@@ -320,6 +354,7 @@ struct txgbe_hw_stats {
 	u64 rx_management_packets;
 	u64 tx_management_packets;
 	u64 rx_management_dropped;
+	u64 rx_dma_drop;
 	u64 rx_drop_packets;
 
 	/* Basic Error */
@@ -566,6 +601,9 @@ struct txgbe_mac_info {
 	s32 (*dmac_config)(struct txgbe_hw *hw);
 	s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
 
+	s32 (*kr_handle)(struct txgbe_hw *hw);
+	void (*bp_down_event)(struct txgbe_hw *hw);
+
 	enum txgbe_mac_type type;
 	u8 addr[ETH_ADDR_LEN];
 	u8 perm_addr[ETH_ADDR_LEN];
@@ -583,9 +621,10 @@ struct txgbe_mac_info {
 	u32 rx_pb_size;
 	u32 max_tx_queues;
 	u32 max_rx_queues;
+	u64 autoc;
+	u64 orig_autoc;  /* cached value of AUTOC */
 	u8  san_mac_rar_index;
 	bool get_link_status;
-	u64 orig_autoc;  /* cached value of AUTOC */
 	bool orig_link_settings_stored;
 	bool autotry_restart;
 	u8 flags;
@@ -613,6 +652,7 @@ struct txgbe_phy_info {
 	s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
 				bool autoneg_wait_to_complete);
 	s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
+	s32 (*get_fw_version)(struct txgbe_hw *hw, u32 *fw_version);
 	s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
 				u8 dev_addr, u8 *data);
 	s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
@@ -648,6 +688,33 @@ struct txgbe_phy_info {
 	bool qsfp_shared_i2c_bus;
 	u32 nw_mng_if_sel;
 	u32 link_mode;
+
+	/* Some features need tri-state capability */
+	u16 ffe_set;
+	u16 ffe_main;
+	u16 ffe_pre;
+	u16 ffe_post;
+};
+
+#define TXGBE_DEVARG_BP_AUTO		"auto_neg"
+#define TXGBE_DEVARG_KR_POLL		"poll"
+#define TXGBE_DEVARG_KR_PRESENT		"present"
+#define TXGBE_DEVARG_KX_SGMII		"sgmii"
+#define TXGBE_DEVARG_FFE_SET		"ffe_set"
+#define TXGBE_DEVARG_FFE_MAIN		"ffe_main"
+#define TXGBE_DEVARG_FFE_PRE		"ffe_pre"
+#define TXGBE_DEVARG_FFE_POST		"ffe_post"
+
+static const char * const txgbe_valid_arguments[] = {
+	TXGBE_DEVARG_BP_AUTO,
+	TXGBE_DEVARG_KR_POLL,
+	TXGBE_DEVARG_KR_PRESENT,
+	TXGBE_DEVARG_KX_SGMII,
+	TXGBE_DEVARG_FFE_SET,
+	TXGBE_DEVARG_FFE_MAIN,
+	TXGBE_DEVARG_FFE_PRE,
+	TXGBE_DEVARG_FFE_POST,
+	NULL
 };
 
 struct txgbe_mbx_stats {
@@ -674,6 +741,7 @@ struct txgbe_mbx_info {
 	struct txgbe_mbx_stats stats;
 	u32 timeout;
 	u32 usec_delay;
+	u32 v2p_mailbox;
 	u16 size;
 };
 
@@ -685,6 +753,13 @@ enum txgbe_isb_idx {
 	TXGBE_ISB_MAX
 };
 
+struct txgbe_devargs {
+	u16 auto_neg;
+	u16 poll;
+	u16 present;
+	u16 sgmii;
+};
+
 struct txgbe_hw {
 	void IOMEM *hw_addr;
 	void *back;
@@ -703,14 +778,18 @@ struct txgbe_hw {
 	u16 subsystem_vendor_id;
 	u8 revision_id;
 	bool adapter_stopped;
+	int api_version;
 	bool allow_unsupported_sfp;
 	bool need_crosstalk_fix;
+	bool dev_start;
+	struct txgbe_devargs devarg;
 
 	uint64_t isb_dma;
 	void IOMEM *isb_mem;
 	u16 nb_rx_queues;
 	u16 nb_tx_queues;
 
+	u32 fw_version;
 	u32 mode;
 	enum txgbe_link_status {
 		TXGBE_LINK_STATUS_NONE = 0,
@@ -726,6 +805,7 @@ struct txgbe_hw {
 	u32 q_rx_regs[128 * 4];
 	u32 q_tx_regs[128 * 4];
 	bool offset_loaded;
+	bool rx_loaded;
 	struct {
 		u64 rx_qp_packets;
 		u64 tx_qp_packets;
@@ -735,6 +815,13 @@ struct txgbe_hw {
 	} qp_last[TXGBE_MAX_QP];
 };
 
+struct txgbe_backplane_ability {
+	u32 next_page;	  /* Next Page (bit0) */
+	u32 link_ability; /* Link Ability (bit[7:0]) */
+	u32 fec_ability;  /* FEC Request (bit1), FEC Enable (bit0) */
+	u32 current_link_mode; /* current link mode for local device */
+};
+
 #include "txgbe_regs.h"
 #include "txgbe_dummy.h"