X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Ftxgbe%2Ftxgbe_ethdev.c;h=90137d0ceb6bb2357fe524250b8be832f4936ec5;hb=9f1b1fbbdd483836f30004ce5db3b99080ebf718;hp=0ce17b18037dd1597065873145e06a40de237631;hpb=ad02aa0343ff0473f6004d3ffd3ac976a10a9d65;p=dpdk.git

diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 0ce17b1803..90137d0ceb 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -7,7 +7,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <rte_common.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_pci.h>
 
 #include <rte_interrupts.h>
 #include <rte_log.h>
@@ -547,6 +547,12 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 	/* Unlock any pending hardware semaphore */
 	txgbe_swfw_lock_reset(hw);
 
+#ifdef RTE_LIB_SECURITY
+	/* Initialize security_ctx only for primary process*/
+	if (txgbe_ipsec_ctx_create(eth_dev))
+		return -ENOMEM;
+#endif
+
 	/* Initialize DCB configuration*/
 	memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 	txgbe_dcb_init(hw, dcb_config);
@@ -1963,6 +1969,10 @@ txgbe_dev_close(struct rte_eth_dev *dev)
 	/* Remove all Traffic Manager configuration */
 	txgbe_tm_conf_uninit(dev);
 
+#ifdef RTE_LIB_SECURITY
+	rte_free(dev->security_ctx);
+#endif
+
 	return ret;
 }
 
@@ -3247,7 +3257,7 @@ txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 		if (!mask)
 			continue;
 
-		reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
+		reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
 		for (j = 0; j < 4; j++) {
 			if (RS8(mask, j, 0x1)) {
 				reta  &= ~(MS32(8 * j, 0xFF));
@@ -3255,7 +3265,7 @@ txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 						8 * j, 0xFF);
 			}
 		}
-		wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
+		wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
 	}
 	adapter->rss_reta_updated = 1;
 
@@ -3288,7 +3298,7 @@ txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 		if (!mask)
 			continue;
 
-		reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
+		reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
 		for (j = 0; j < 4; j++) {
 			if (RS8(mask, j, 0x1))
 				reta_conf[idx].reta[shift + j] =
@@ -4111,7 +4121,7 @@ txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 
 	hw = TXGBE_DEV_HW(dev);
 	mc_addr_list = (u8 *)mc_addr_set;
-	return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
+	return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
 					 txgbe_dev_addr_list_itr, TRUE);
 }
 
@@ -4514,6 +4524,7 @@ txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
 {
 	switch (mac_type) {
 	case txgbe_mac_raptor:
+	case txgbe_mac_raptor_vf:
 		return 1;
 	default:
 		return 0;
@@ -5215,6 +5226,7 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {
 	.timesync_write_time        = txgbe_timesync_write_time,
 	.udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
 	.udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
+	.tm_ops_get                 = txgbe_tm_ops_get,
 	.tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
 };