X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Ftxgbe%2Ftxgbe_rxtx.h;h=203bdeb882a4b99dd72b008c2eea08afb803ea23;hb=3a123ba60a7158ec34bc680fb8d7c2fb7db07c9d;hp=27f2c576a759db35fba0cd1e5476514ebf2fd3ed;hpb=aa55a55b207fdb932e1a883b83d8aee6c3044063;p=dpdk.git diff --git a/drivers/net/txgbe/txgbe_rxtx.h b/drivers/net/txgbe/txgbe_rxtx.h index 27f2c576a7..203bdeb882 100644 --- a/drivers/net/txgbe/txgbe_rxtx.h +++ b/drivers/net/txgbe/txgbe_rxtx.h @@ -50,6 +50,100 @@ struct txgbe_rx_desc { #define TXGBE_RXD_HDRADDR(rxd, v) \ (((volatile __le64 *)(rxd))[1] = cpu_to_le64(v)) +/* @txgbe_rx_desc.dw0 */ +#define TXGBE_RXD_RSSTYPE(dw) RS(dw, 0, 0xF) +#define TXGBE_RSSTYPE_NONE 0 +#define TXGBE_RSSTYPE_IPV4TCP 1 +#define TXGBE_RSSTYPE_IPV4 2 +#define TXGBE_RSSTYPE_IPV6TCP 3 +#define TXGBE_RSSTYPE_IPV4SCTP 4 +#define TXGBE_RSSTYPE_IPV6 5 +#define TXGBE_RSSTYPE_IPV6SCTP 6 +#define TXGBE_RSSTYPE_IPV4UDP 7 +#define TXGBE_RSSTYPE_IPV6UDP 8 +#define TXGBE_RSSTYPE_FDIR 15 +#define TXGBE_RXD_SECTYPE(dw) RS(dw, 4, 0x3) +#define TXGBE_RXD_SECTYPE_NONE LS(0, 4, 0x3) +#define TXGBE_RXD_SECTYPE_LINKSEC LS(1, 4, 0x3) +#define TXGBE_RXD_SECTYPE_IPSECESP LS(2, 4, 0x3) +#define TXGBE_RXD_SECTYPE_IPSECAH LS(3, 4, 0x3) +#define TXGBE_RXD_TPIDSEL(dw) RS(dw, 6, 0x7) +#define TXGBE_RXD_PTID(dw) RS(dw, 9, 0xFF) +#define TXGBE_RXD_RSCCNT(dw) RS(dw, 17, 0xF) +#define TXGBE_RXD_HDRLEN(dw) RS(dw, 21, 0x3FF) +#define TXGBE_RXD_SPH MS(31, 0x1) + +/* @txgbe_rx_desc.dw1 */ +/** bit 0-31, as rss hash when **/ +#define TXGBE_RXD_RSSHASH(rxd) ((rxd)->qw0.dw1) + +/** bit 0-31, as ip csum when **/ +#define TXGBE_RXD_IPID(rxd) ((rxd)->qw0.hi.ipid) +#define TXGBE_RXD_CSUM(rxd) ((rxd)->qw0.hi.csum) + +/** bit 0-31, as fdir id when **/ +#define TXGBE_RXD_FDIRID(rxd) ((rxd)->qw0.hi.dw1) + +/* @txgbe_rx_desc.dw2 */ +#define TXGBE_RXD_STATUS(rxd) ((rxd)->qw1.lo.status) +/** bit 0-1 **/ +#define TXGBE_RXD_STAT_DD MS(0, 0x1) /* Descriptor Done */ +#define TXGBE_RXD_STAT_EOP MS(1, 0x1) /* End of Packet */ +/** bit 2-31, when EOP=0 **/ +#define TXGBE_RXD_NEXTP_RESV(v) LS(v, 2, 0x3) +#define TXGBE_RXD_NEXTP(dw) RS(dw, 4, 0xFFFF) /* Next Descriptor */ +/** bit 2-31, when EOP=1 **/ +#define TXGBE_RXD_PKT_CLS_MASK MS(2, 0x7) /* Packet Class */ +#define TXGBE_RXD_PKT_CLS_TC_RSS LS(0, 2, 0x7) /* RSS Hash */ +#define TXGBE_RXD_PKT_CLS_FLM LS(1, 2, 0x7) /* FDir Match */ +#define TXGBE_RXD_PKT_CLS_SYN LS(2, 2, 0x7) /* TCP Sync */ +#define TXGBE_RXD_PKT_CLS_5TUPLE LS(3, 2, 0x7) /* 5 Tuple */ +#define TXGBE_RXD_PKT_CLS_ETF LS(4, 2, 0x7) /* Ethertype Filter */ +#define TXGBE_RXD_STAT_VLAN MS(5, 0x1) /* IEEE VLAN Packet */ +#define TXGBE_RXD_STAT_UDPCS MS(6, 0x1) /* UDP xsum calculated */ +#define TXGBE_RXD_STAT_L4CS MS(7, 0x1) /* L4 xsum calculated */ +#define TXGBE_RXD_STAT_IPCS MS(8, 0x1) /* IP xsum calculated */ +#define TXGBE_RXD_STAT_PIF MS(9, 0x1) /* Non-unicast address */ +#define TXGBE_RXD_STAT_EIPCS MS(10, 0x1) /* Encap IP xsum calculated */ +#define TXGBE_RXD_STAT_VEXT MS(11, 0x1) /* Multi-VLAN */ +#define TXGBE_RXD_STAT_IPV6EX MS(12, 0x1) /* IPv6 with option header */ +#define TXGBE_RXD_STAT_LLINT MS(13, 0x1) /* Pkt caused LLI */ +#define TXGBE_RXD_STAT_1588 MS(14, 0x1) /* IEEE1588 Time Stamp */ +#define TXGBE_RXD_STAT_SECP MS(15, 0x1) /* Security Processing */ +#define TXGBE_RXD_STAT_LB MS(16, 0x1) /* Loopback Status */ +/*** bit 17-30, when PTYPE=IP ***/ +#define TXGBE_RXD_STAT_BMC MS(17, 0x1) /* PTYPE=IP, BMC status */ +#define TXGBE_RXD_ERR_FDIR_LEN MS(20, 0x1) /* FDIR Length error */ +#define TXGBE_RXD_ERR_FDIR_DROP MS(21, 0x1) /* FDIR Drop error */ +#define TXGBE_RXD_ERR_FDIR_COLL MS(22, 0x1) /* FDIR Collision error */ +#define TXGBE_RXD_ERR_HBO MS(23, 0x1) /* Header Buffer Overflow */ +#define TXGBE_RXD_ERR_EIPCS MS(26, 0x1) /* Encap IP header error */ +#define TXGBE_RXD_ERR_SECERR MS(27, 0x1) /* macsec or ipsec error */ +#define TXGBE_RXD_ERR_RXE MS(29, 0x1) /* Any MAC Error */ +#define TXGBE_RXD_ERR_L4CS MS(30, 0x1) /* TCP/UDP xsum error */ +#define TXGBE_RXD_ERR_IPCS MS(31, 0x1) /* IP xsum error */ +#define TXGBE_RXD_ERR_CSUM(dw) RS(dw, 30, 0x3) +/*** bit 17-30, when PTYPE=FCOE ***/ +#define TXGBE_RXD_STAT_FCOEFS MS(17, 0x1) /* PTYPE=FCOE, FCoE EOF/SOF */ +#define TXGBE_RXD_FCSTAT_MASK MS(18, 0x3) /* FCoE Pkt Stat */ +#define TXGBE_RXD_FCSTAT_NOMTCH LS(0, 18, 0x3) /* No Ctxt Match */ +#define TXGBE_RXD_FCSTAT_NODDP LS(1, 18, 0x3) /* Ctxt w/o DDP */ +#define TXGBE_RXD_FCSTAT_FCPRSP LS(2, 18, 0x3) /* Recv. FCP_RSP */ +#define TXGBE_RXD_FCSTAT_DDP LS(3, 18, 0x3) /* Ctxt w/ DDP */ +#define TXGBE_RXD_FCERR_MASK MS(20, 0x7) /* FCERR */ +#define TXGBE_RXD_FCERR_0 LS(0, 20, 0x7) +#define TXGBE_RXD_FCERR_1 LS(1, 20, 0x7) +#define TXGBE_RXD_FCERR_2 LS(2, 20, 0x7) +#define TXGBE_RXD_FCERR_3 LS(3, 20, 0x7) +#define TXGBE_RXD_FCERR_4 LS(4, 20, 0x7) +#define TXGBE_RXD_FCERR_5 LS(5, 20, 0x7) +#define TXGBE_RXD_FCERR_6 LS(6, 20, 0x7) +#define TXGBE_RXD_FCERR_7 LS(7, 20, 0x7) + +/* @txgbe_rx_desc.dw3 */ +#define TXGBE_RXD_LENGTH(rxd) ((rxd)->qw1.hi.len) +#define TXGBE_RXD_VLAN(rxd) ((rxd)->qw1.hi.tag) + /***************************************************************************** * Transmit Descriptor *****************************************************************************/ @@ -145,6 +239,8 @@ struct txgbe_tx_desc { #define RX_RING_SZ ((TXGBE_RING_DESC_MAX + RTE_PMD_TXGBE_RX_MAX_BURST) * \ sizeof(struct txgbe_rx_desc)) +#define rte_packet_prefetch(p) rte_prefetch1(p) + #define RTE_TXGBE_REGISTER_POLL_WAIT_10_MS 10 #define RTE_TXGBE_WAIT_100_US 100 @@ -197,6 +293,10 @@ struct txgbe_rx_queue { uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */ uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */ uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ +#ifdef RTE_LIB_SECURITY + uint8_t using_ipsec; + /**< indicates that IPsec RX feature is in use */ +#endif uint16_t rx_free_thresh; /**< max free RX desc to hold. */ uint16_t queue_id; /**< RX queue index. */ uint16_t reg_idx; /**< RX queue register index. */ @@ -206,6 +306,8 @@ struct txgbe_rx_queue { uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */ uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */ uint8_t rx_deferred_start; /**< not in global dev start. */ + /** flags to set in mbuf when a vlan is detected. */ + uint64_t vlan_flags; uint64_t offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */ /** need to alloc dummy mbuf, for wraparound when scanning hw ring */ struct rte_mbuf fake_mbuf; @@ -213,6 +315,50 @@ struct txgbe_rx_queue { struct rte_mbuf *rx_stage[RTE_PMD_TXGBE_RX_MAX_BURST * 2]; }; +/** + * TXGBE CTX Constants + */ +enum txgbe_ctx_num { + TXGBE_CTX_0 = 0, /**< CTX0 */ + TXGBE_CTX_1 = 1, /**< CTX1 */ + TXGBE_CTX_NUM = 2, /**< CTX NUMBER */ +}; + +/** Offload features */ +union txgbe_tx_offload { + uint64_t data[2]; + struct { + uint64_t ptid:8; /**< Packet Type Identifier. */ + uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ + uint64_t l3_len:9; /**< L3 (IP) Header Length. */ + uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ + uint64_t tso_segsz:16; /**< TCP TSO segment size */ + uint64_t vlan_tci:16; + /**< VLAN Tag Control Identifier (CPU order). */ + + /* fields for TX offloading of tunnels */ + uint64_t outer_tun_len:8; /**< Outer TUN (Tunnel) Hdr Length. */ + uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */ + uint64_t outer_l3_len:16; /**< Outer L3 (IP) Hdr Length. */ +#ifdef RTE_LIB_SECURITY + /* inline ipsec related*/ + uint64_t sa_idx:8; /**< TX SA database entry index */ + uint64_t sec_pad_len:4; /**< padding length */ +#endif + }; +}; + +/** + * Structure to check if new context need be built + */ +struct txgbe_ctx_info { + uint64_t flags; /**< ol_flags for context build. */ + /**< tx offload: vlan, tso, l2-l3-l4 lengths. */ + union txgbe_tx_offload tx_offload; + /** compare mask for tx offload. */ + union txgbe_tx_offload tx_offload_mask; +}; + /** * Structure associated with each TX queue. */ @@ -234,6 +380,9 @@ struct txgbe_tx_queue { * this value. */ uint16_t tx_free_thresh; + /** Index to last TX descriptor to have been cleaned. */ + uint16_t last_desc_cleaned; + /** Total number of TX descriptors ready to be allocated. */ uint16_t nb_tx_free; uint16_t tx_next_dd; /**< next desc to scan for DD bit */ uint16_t queue_id; /**< TX queue index. */ @@ -243,8 +392,15 @@ struct txgbe_tx_queue { uint8_t hthresh; /**< Host threshold register. */ uint8_t wthresh; /**< Write-back threshold reg. */ uint64_t offloads; /* Tx offload flags of DEV_TX_OFFLOAD_* */ + uint32_t ctx_curr; /**< Hardware context states. */ + /** Hardware context0 history. */ + struct txgbe_ctx_info ctx_cache[TXGBE_CTX_NUM]; const struct txgbe_txq_ops *ops; /**< txq ops */ uint8_t tx_deferred_start; /**< not in global dev start. */ +#ifdef RTE_LIB_SECURITY + uint8_t using_ipsec; + /**< indicates that IPsec TX feature is in use */ +#endif }; struct txgbe_txq_ops { @@ -260,6 +416,7 @@ struct txgbe_txq_ops { void txgbe_set_tx_function(struct rte_eth_dev *dev, struct txgbe_tx_queue *txq); void txgbe_set_rx_function(struct rte_eth_dev *dev); +int txgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt); uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev); uint64_t txgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);