X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fraw%2Fntb%2Fntb_hw_intel.h;h=c61a2a8a6219ebccf8368cfd19a8faa3855fc0f8;hb=675a6c18746694a8e19a0256b16bd6b3e8dcbfd2;hp=4d1e64504c2c5df2842c0aff502be4f06f9f4ed8;hpb=034c328eb0254e1577ccdf3274acbe80d137b5a7;p=dpdk.git

diff --git a/drivers/raw/ntb/ntb_hw_intel.h b/drivers/raw/ntb/ntb_hw_intel.h
index 4d1e64504c..c61a2a8a62 100644
--- a/drivers/raw/ntb/ntb_hw_intel.h
+++ b/drivers/raw/ntb/ntb_hw_intel.h
@@ -22,7 +22,7 @@
 #define NTB_LNK_STA_SPEED(x)		((x) & NTB_LNK_STA_SPEED_MASK)
 #define NTB_LNK_STA_WIDTH(x)		(((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
 
-/* Intel Skylake Xeon hardware */
+/* Intel Xeon hardware */
 #define XEON_IMBAR1SZ_OFFSET		0x00d0
 #define XEON_IMBAR2SZ_OFFSET		0x00d1
 #define XEON_EMBAR1SZ_OFFSET		0x00d2
@@ -31,7 +31,13 @@
 #define XEON_DEVSTS_OFFSET		0x009a
 #define XEON_UNCERRSTS_OFFSET		0x014c
 #define XEON_CORERRSTS_OFFSET		0x0158
-#define XEON_LINK_STATUS_OFFSET		0x01a2
+#define XEON_GEN3_LINK_STATUS_OFFSET	0x01a2
+/* Link status and PPD are in MMIO but not config space for Gen4 NTB */
+#define XEON_GEN4_PPD0_OFFSET		0xb0d4
+#define XEON_GEN4_PPD1_OFFSET		0xb4c0
+#define XEON_GEN4_LINK_CTRL_OFFSET	0xb050
+#define XEON_GEN4_LINK_STATUS_OFFSET	0xb052
+#define XEON_GEN4_LINK_CTRL_LINK_DIS	0x0010
 
 #define XEON_NTBCNTL_OFFSET		0x0000
 #define XEON_BAR_INTERVAL_OFFSET	0x0010
@@ -39,13 +45,18 @@
 #define XEON_IMBAR1XLMT_OFFSET		0x0018		/* SBAR2LMT */
 #define XEON_IMBAR2XBASE_OFFSET		0x0020		/* SBAR4XLAT */
 #define XEON_IMBAR2XLMT_OFFSET		0x0028		/* SBAR4LMT */
+#define XEON_GEN4_XBASEIDX_INTERVAL	0x0002
+#define XEON_GEN4_IM1XBASEIDX_OFFSET	0x0074
+#define XEON_GEN4_IM2XBASEIDX_OFFSET	0x0076
 #define XEON_IM_INT_STATUS_OFFSET	0x0040
 #define XEON_IM_INT_DISABLE_OFFSET	0x0048
 #define XEON_IM_SPAD_OFFSET		0x0080		/* SPAD */
+#define XEON_GEN3_B2B_SPAD_OFFSET	0x0180		/* GEN3 B2B SPAD */
+#define XEON_GEN4_B2B_SPAD_OFFSET	0x8080		/* GEN4 B2B SPAD */
 #define XEON_USMEMMISS_OFFSET		0x0070
-#define XEON_INTVEC_OFFSET		0x00d0
+#define XEON_GEN3_INTVEC_OFFSET		0x00d0
+#define XEON_GEN4_INTVEC_OFFSET		0x0050
 #define XEON_IM_DOORBELL_OFFSET		0x0100		/* SDOORBELL0 */
-#define XEON_B2B_SPAD_OFFSET		0x0180		/* B2B SPAD */
 #define XEON_EMBAR0XBASE_OFFSET		0x4008		/* B2B_XLAT */
 #define XEON_EMBAR1XBASE_OFFSET		0x4010		/* PBAR2XLAT */
 #define XEON_EMBAR1XLMT_OFFSET		0x4018		/* PBAR2LMT */
@@ -70,6 +81,14 @@
 #define XEON_PPD_DEV_DSD		0x10
 #define XEON_PPD_SPLIT_BAR_MASK		0x40
 
+#define XEON_GEN4_PPD_CONN_MASK		0x0300
+#define XEON_GEN4_PPD_CONN_B2B		0x0200
+#define XEON_GEN4_PPD_DEV_MASK		0x1000
+#define XEON_GEN4_PPD_DEV_DSD		0x1000
+#define XEON_GEN4_PPD_DEV_USD		0x0000
+#define XEON_GEN4_PPD_LINKTRN		0x0008
+#define XEON_GEN4_SLOTSTS		0xb05a
+#define XEON_GEN4_SLOTSTS_DLLSCS	0x100
 
 #define XEON_MW_COUNT			2