X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fraw%2Focteontx2_ep%2Fotx2_ep_rawdev.h;h=dab2fb7541c8692e64a479d266b347bbc02b768f;hb=07d4bde1c0e811ae60144ae74337237e6fb47e29;hp=a01f48d32c5e3702093c314c0bff917dfdd757f2;hpb=f2cccd860ce0e3041480a9b56efd929aef0991ee;p=dpdk.git

diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
index a01f48d32c..dab2fb7541 100644
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
@@ -8,6 +8,10 @@
 #include <rte_byteorder.h>
 #include <rte_spinlock.h>
 
+/* IQ instruction req types */
+#define SDP_REQTYPE_NONE             (0)
+#define SDP_REQTYPE_NORESP           (1)
+#define SDP_REQTYPE_NORESP_GATHER    (2)
 
 /* Input Request Header format */
 struct sdp_instr_irh {
@@ -128,6 +132,13 @@ struct sdp_instr_list {
 };
 #define SDP_IQREQ_LIST_SIZE	(sizeof(struct sdp_instr_list))
 
+/* Input Queue statistics. Each input queue has four stats fields. */
+struct sdp_iq_stats {
+	uint64_t instr_posted; /* Instructions posted to this queue. */
+	uint64_t instr_processed; /* Instructions processed in this queue. */
+	uint64_t instr_dropped; /* Instructions that could not be processed */
+};
+
 /* Structure to define the configuration attributes for each Input queue. */
 struct sdp_iq_config {
 	/* Max number of IQs available */
@@ -195,6 +206,9 @@ struct sdp_instr_queue {
 	/* Number of instructions pending to be posted to OCTEON TX2. */
 	uint32_t fill_cnt;
 
+	/* Statistics for this input queue. */
+	struct sdp_iq_stats stats;
+
 	/* DMA mapped base address of the input descriptor ring. */
 	uint64_t base_addr_dma;
 
@@ -265,6 +279,18 @@ struct sdp_recv_buffer {
 };
 #define SDP_DROQ_RECVBUF_SIZE	(sizeof(struct sdp_recv_buffer))
 
+/* DROQ statistics. Each output queue has four stats fields. */
+struct sdp_droq_stats {
+	/* Number of packets received in this queue. */
+	uint64_t pkts_received;
+
+	/* Bytes received by this queue. */
+	uint64_t bytes_received;
+
+	/* Num of failures of rte_pktmbuf_alloc() */
+	uint64_t rx_alloc_failure;
+};
+
 /* Structure to define the configuration attributes for each Output queue. */
 struct sdp_oq_config {
 	/* Max number of OQs available */
@@ -331,6 +357,9 @@ struct sdp_droq {
 	 */
 	void *pkts_sent_reg;
 
+	/* Statistics for this DROQ. */
+	struct sdp_droq_stats stats;
+
 	/* DMA mapped address of the DROQ descriptor ring. */
 	size_t desc_ring_dma;
 
@@ -380,6 +409,8 @@ struct sdp_fn_list {
 	void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
 
 	int (*setup_device_regs)(struct sdp_device *sdpvf);
+	uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
+
 	void (*enable_io_queues)(struct sdp_device *sdpvf);
 	void (*disable_io_queues)(struct sdp_device *sdpvf);
 
@@ -458,4 +489,11 @@ int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
 int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
 int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
 
+int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
+		       unsigned int count, rte_rawdev_obj_t context);
+int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
+		       unsigned int count, rte_rawdev_obj_t context);
+
+int sdp_rawdev_selftest(uint16_t dev_id);
+
 #endif /* _OTX2_EP_RAWDEV_H_ */