X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fregex%2Fmlx5%2Fmlx5_regex.h;h=484819c38c30042cbd391ee4ec76580114352afc;hb=762bfccc8abfb44995e4884136f7838fb500b507;hp=f17b4f81bd5c5294ebc52b1db9a8afd6771a8400;hpb=e3dbbf718ebc7cccc7b0a5f524f2250f69caff31;p=dpdk.git diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index f17b4f81bd..484819c38c 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -7,14 +7,51 @@ #include +#include +#include + +#include +#include +#include + +#include "mlx5_rxp.h" + struct mlx5_regex_sq { - uint32_t nb_desc; /* Number of desc for this object. */ + uint16_t log_nb_desc; /* Log 2 number of desc for this object. */ + struct mlx5_devx_sq sq_obj; /* The SQ DevX object. */ + size_t pi, db_pi; + size_t ci; + uint32_t sqn; +}; + +struct mlx5_regex_cq { + uint32_t log_nb_desc; /* Log 2 number of desc for this object. */ + struct mlx5_devx_cq cq_obj; /* The CQ DevX object. */ + size_t ci; }; struct mlx5_regex_qp { uint32_t flags; /* QP user flags. */ uint32_t nb_desc; /* Total number of desc for this qp. */ struct mlx5_regex_sq *sqs; /* Pointer to sq array. */ + uint16_t nb_obj; /* Number of sq objects. */ + struct mlx5_regex_cq cq; /* CQ struct. */ + uint32_t free_sqs; + struct mlx5_regex_job *jobs; + struct ibv_mr *metadata; + struct ibv_mr *outputs; + size_t ci, pi; + struct mlx5_mr_ctrl mr_ctrl; +}; + +struct mlx5_regex_db { + void *ptr; /* Pointer to the db memory. */ + uint32_t len; /* The memory len. */ + bool active; /* Active flag. */ + uint8_t db_assigned_to_eng_num; + /**< To which engine the db is connected. */ + struct mlx5_regex_umem umem; + /**< The umem struct. */ }; struct mlx5_regex_priv { @@ -25,18 +62,50 @@ struct mlx5_regex_priv { uint16_t nb_queues; /* Number of queues. */ struct mlx5_regex_qp *qps; /* Pointer to the qp array. */ uint16_t nb_max_matches; /* Max number of matches. */ + enum mlx5_rxp_program_mode prog_mode; + struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES + + MLX5_RXP_EM_COUNT]; + uint32_t nb_engines; /* Number of RegEx engines. */ + struct mlx5dv_devx_uar *uar; /* UAR object. */ + struct ibv_pd *pd; + struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ + uint8_t is_bf2; /* The device is BF2 device. */ }; +/* mlx5_regex.c */ +int mlx5_regex_start(struct rte_regexdev *dev); +int mlx5_regex_stop(struct rte_regexdev *dev); +int mlx5_regex_close(struct rte_regexdev *dev); + /* mlx5_rxp.c */ int mlx5_regex_info_get(struct rte_regexdev *dev, struct rte_regexdev_info *info); int mlx5_regex_configure(struct rte_regexdev *dev, const struct rte_regexdev_config *cfg); +int mlx5_regex_rules_db_import(struct rte_regexdev *dev, + const char *rule_db, uint32_t rule_db_len); /* mlx5_regex_devx.c */ int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id, uint32_t addr, uint32_t data); int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id, uint32_t addr, uint32_t *data); +int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine); +int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine); +int mlx5_devx_regex_database_program(void *ctx, uint8_t engine, + uint32_t umem_id, uint64_t umem_offset); + +/* mlx5_regex_control.c */ +int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, + const struct rte_regexdev_qp_conf *cfg); + +/* mlx5_regex_fastpath.c */ +int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id); +void mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, + uint32_t qp_id); +uint16_t mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, + struct rte_regex_ops **ops, uint16_t nb_ops); +uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, + struct rte_regex_ops **ops, uint16_t nb_ops); #endif /* MLX5_REGEX_H */