X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Fethdev%2Frte_ethdev.c;h=90e153c7b1a78bb5d69c87a5b9f941f20ce305bf;hb=6e858b4d9244cf53505589673755ab18ac2a4a83;hp=4ea5a657e003650d25b5631a0b6ad48af47d53fb;hpb=93e441c9a0c13cade820916979337a4269f67f7c;p=dpdk.git diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 4ea5a657e0..90e153c7b1 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -101,9 +101,6 @@ static const struct rte_eth_xstats_name_off eth_dev_txq_stats_strings[] = { #define RTE_NB_TXQ_STATS RTE_DIM(eth_dev_txq_stats_strings) #define RTE_RX_OFFLOAD_BIT2STR(_name) \ - { DEV_RX_OFFLOAD_##_name, #_name } - -#define RTE_ETH_RX_OFFLOAD_BIT2STR(_name) \ { RTE_ETH_RX_OFFLOAD_##_name, #_name } static const struct { @@ -128,14 +125,14 @@ static const struct { RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM), RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), RTE_RX_OFFLOAD_BIT2STR(RSS_HASH), - RTE_ETH_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT), + RTE_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT), }; #undef RTE_RX_OFFLOAD_BIT2STR #undef RTE_ETH_RX_OFFLOAD_BIT2STR #define RTE_TX_OFFLOAD_BIT2STR(_name) \ - { DEV_TX_OFFLOAD_##_name, #_name } + { RTE_ETH_TX_OFFLOAD_##_name, #_name } static const struct { uint64_t offload; @@ -174,6 +171,8 @@ static const struct { {RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP, "RUNTIME_RX_QUEUE_SETUP"}, {RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP, "RUNTIME_TX_QUEUE_SETUP"}, {RTE_ETH_DEV_CAPA_RXQ_SHARE, "RXQ_SHARE"}, + {RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP, "FLOW_RULE_KEEP"}, + {RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP, "FLOW_SHARED_OBJECT_KEEP"}, }; /** @@ -760,10 +759,13 @@ rte_eth_dev_owner_delete(const uint64_t owner_id) rte_spinlock_lock(ð_dev_shared_data->ownership_lock); if (eth_is_valid_owner_id(owner_id)) { - for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) - if (rte_eth_devices[port_id].data->owner.id == owner_id) - memset(&rte_eth_devices[port_id].data->owner, 0, + for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { + struct rte_eth_dev_data *data = + rte_eth_devices[port_id].data; + if (data != NULL && data->owner.id == owner_id) + memset(&data->owner, 0, sizeof(struct rte_eth_dev_owner)); + } RTE_ETHDEV_LOG(NOTICE, "All port owners owned by %016"PRIx64" identifier have removed\n", owner_id); @@ -892,6 +894,17 @@ rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id) return -ENODEV; } +struct rte_eth_dev * +rte_eth_dev_get_by_name(const char *name) +{ + uint16_t pid; + + if (rte_eth_dev_get_port_by_name(name, &pid)) + return NULL; + + return &rte_eth_devices[pid]; +} + static int eth_err(uint16_t port_id, int ret) { @@ -1182,32 +1195,32 @@ uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex) { switch (speed) { - case ETH_SPEED_NUM_10M: - return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD; - case ETH_SPEED_NUM_100M: - return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD; - case ETH_SPEED_NUM_1G: - return ETH_LINK_SPEED_1G; - case ETH_SPEED_NUM_2_5G: - return ETH_LINK_SPEED_2_5G; - case ETH_SPEED_NUM_5G: - return ETH_LINK_SPEED_5G; - case ETH_SPEED_NUM_10G: - return ETH_LINK_SPEED_10G; - case ETH_SPEED_NUM_20G: - return ETH_LINK_SPEED_20G; - case ETH_SPEED_NUM_25G: - return ETH_LINK_SPEED_25G; - case ETH_SPEED_NUM_40G: - return ETH_LINK_SPEED_40G; - case ETH_SPEED_NUM_50G: - return ETH_LINK_SPEED_50G; - case ETH_SPEED_NUM_56G: - return ETH_LINK_SPEED_56G; - case ETH_SPEED_NUM_100G: - return ETH_LINK_SPEED_100G; - case ETH_SPEED_NUM_200G: - return ETH_LINK_SPEED_200G; + case RTE_ETH_SPEED_NUM_10M: + return duplex ? RTE_ETH_LINK_SPEED_10M : RTE_ETH_LINK_SPEED_10M_HD; + case RTE_ETH_SPEED_NUM_100M: + return duplex ? RTE_ETH_LINK_SPEED_100M : RTE_ETH_LINK_SPEED_100M_HD; + case RTE_ETH_SPEED_NUM_1G: + return RTE_ETH_LINK_SPEED_1G; + case RTE_ETH_SPEED_NUM_2_5G: + return RTE_ETH_LINK_SPEED_2_5G; + case RTE_ETH_SPEED_NUM_5G: + return RTE_ETH_LINK_SPEED_5G; + case RTE_ETH_SPEED_NUM_10G: + return RTE_ETH_LINK_SPEED_10G; + case RTE_ETH_SPEED_NUM_20G: + return RTE_ETH_LINK_SPEED_20G; + case RTE_ETH_SPEED_NUM_25G: + return RTE_ETH_LINK_SPEED_25G; + case RTE_ETH_SPEED_NUM_40G: + return RTE_ETH_LINK_SPEED_40G; + case RTE_ETH_SPEED_NUM_50G: + return RTE_ETH_LINK_SPEED_50G; + case RTE_ETH_SPEED_NUM_56G: + return RTE_ETH_LINK_SPEED_56G; + case RTE_ETH_SPEED_NUM_100G: + return RTE_ETH_LINK_SPEED_100G; + case RTE_ETH_SPEED_NUM_200G: + return RTE_ETH_LINK_SPEED_200G; default: return 0; } @@ -1528,7 +1541,7 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, * If LRO is enabled, check that the maximum aggregated packet * size is supported by the configured device. */ - if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) { + if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) { uint32_t max_rx_pktlen; uint32_t overhead_len; @@ -1585,12 +1598,12 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, } /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */ - if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) && - (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) { + if (((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) == 0) && + (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH)) { RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested\n", port_id, - rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH)); + rte_eth_dev_rx_offload_name(RTE_ETH_RX_OFFLOAD_RSS_HASH)); ret = -EINVAL; goto rollback; } @@ -2213,7 +2226,7 @@ rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, * size is supported by the configured device. */ /* Get the real Ethernet overhead length */ - if (local_conf.offloads & DEV_RX_OFFLOAD_TCP_LRO) { + if (local_conf.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) { uint32_t overhead_len; uint32_t max_rx_pktlen; int ret; @@ -2793,21 +2806,21 @@ const char * rte_eth_link_speed_to_str(uint32_t link_speed) { switch (link_speed) { - case ETH_SPEED_NUM_NONE: return "None"; - case ETH_SPEED_NUM_10M: return "10 Mbps"; - case ETH_SPEED_NUM_100M: return "100 Mbps"; - case ETH_SPEED_NUM_1G: return "1 Gbps"; - case ETH_SPEED_NUM_2_5G: return "2.5 Gbps"; - case ETH_SPEED_NUM_5G: return "5 Gbps"; - case ETH_SPEED_NUM_10G: return "10 Gbps"; - case ETH_SPEED_NUM_20G: return "20 Gbps"; - case ETH_SPEED_NUM_25G: return "25 Gbps"; - case ETH_SPEED_NUM_40G: return "40 Gbps"; - case ETH_SPEED_NUM_50G: return "50 Gbps"; - case ETH_SPEED_NUM_56G: return "56 Gbps"; - case ETH_SPEED_NUM_100G: return "100 Gbps"; - case ETH_SPEED_NUM_200G: return "200 Gbps"; - case ETH_SPEED_NUM_UNKNOWN: return "Unknown"; + case RTE_ETH_SPEED_NUM_NONE: return "None"; + case RTE_ETH_SPEED_NUM_10M: return "10 Mbps"; + case RTE_ETH_SPEED_NUM_100M: return "100 Mbps"; + case RTE_ETH_SPEED_NUM_1G: return "1 Gbps"; + case RTE_ETH_SPEED_NUM_2_5G: return "2.5 Gbps"; + case RTE_ETH_SPEED_NUM_5G: return "5 Gbps"; + case RTE_ETH_SPEED_NUM_10G: return "10 Gbps"; + case RTE_ETH_SPEED_NUM_20G: return "20 Gbps"; + case RTE_ETH_SPEED_NUM_25G: return "25 Gbps"; + case RTE_ETH_SPEED_NUM_40G: return "40 Gbps"; + case RTE_ETH_SPEED_NUM_50G: return "50 Gbps"; + case RTE_ETH_SPEED_NUM_56G: return "56 Gbps"; + case RTE_ETH_SPEED_NUM_100G: return "100 Gbps"; + case RTE_ETH_SPEED_NUM_200G: return "200 Gbps"; + case RTE_ETH_SPEED_NUM_UNKNOWN: return "Unknown"; default: return "Invalid"; } } @@ -2831,14 +2844,14 @@ rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link) return -EINVAL; } - if (eth_link->link_status == ETH_LINK_DOWN) + if (eth_link->link_status == RTE_ETH_LINK_DOWN) return snprintf(str, len, "Link down"); else return snprintf(str, len, "Link up at %s %s %s", rte_eth_link_speed_to_str(eth_link->link_speed), - (eth_link->link_duplex == ETH_LINK_FULL_DUPLEX) ? + (eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? "FDX" : "HDX", - (eth_link->link_autoneg == ETH_LINK_AUTONEG) ? + (eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ? "Autoneg" : "Fixed"); } @@ -3728,6 +3741,13 @@ rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu) return ret; } + if (dev->data->dev_configured == 0) { + RTE_ETHDEV_LOG(ERR, + "Port %u must be configured before MTU set\n", + port_id); + return -EINVAL; + } + ret = (*dev->dev_ops->mtu_set)(dev, mtu); if (ret == 0) dev->data->mtu = mtu; @@ -3745,7 +3765,7 @@ rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on) dev = &rte_eth_devices[port_id]; if (!(dev->data->dev_conf.rxmode.offloads & - DEV_RX_OFFLOAD_VLAN_FILTER)) { + RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) { RTE_ETHDEV_LOG(ERR, "Port %u: VLAN-filtering disabled\n", port_id); return -ENOSYS; @@ -3832,44 +3852,44 @@ rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask) dev_offloads = orig_offloads; /* check which option changed by application */ - cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD); - org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP); + cur = !!(offload_mask & RTE_ETH_VLAN_STRIP_OFFLOAD); + org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); if (cur != org) { if (cur) - dev_offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; + dev_offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; else - dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; - mask |= ETH_VLAN_STRIP_MASK; + dev_offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; + mask |= RTE_ETH_VLAN_STRIP_MASK; } - cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD); - org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER); + cur = !!(offload_mask & RTE_ETH_VLAN_FILTER_OFFLOAD); + org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER); if (cur != org) { if (cur) - dev_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; + dev_offloads |= RTE_ETH_RX_OFFLOAD_VLAN_FILTER; else - dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER; - mask |= ETH_VLAN_FILTER_MASK; + dev_offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_FILTER; + mask |= RTE_ETH_VLAN_FILTER_MASK; } - cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD); - org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND); + cur = !!(offload_mask & RTE_ETH_VLAN_EXTEND_OFFLOAD); + org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND); if (cur != org) { if (cur) - dev_offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND; + dev_offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; else - dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_EXTEND; - mask |= ETH_VLAN_EXTEND_MASK; + dev_offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; + mask |= RTE_ETH_VLAN_EXTEND_MASK; } - cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD); - org = !!(dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP); + cur = !!(offload_mask & RTE_ETH_QINQ_STRIP_OFFLOAD); + org = !!(dev_offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP); if (cur != org) { if (cur) - dev_offloads |= DEV_RX_OFFLOAD_QINQ_STRIP; + dev_offloads |= RTE_ETH_RX_OFFLOAD_QINQ_STRIP; else - dev_offloads &= ~DEV_RX_OFFLOAD_QINQ_STRIP; - mask |= ETH_QINQ_STRIP_MASK; + dev_offloads &= ~RTE_ETH_RX_OFFLOAD_QINQ_STRIP; + mask |= RTE_ETH_QINQ_STRIP_MASK; } /*no change*/ @@ -3914,17 +3934,17 @@ rte_eth_dev_get_vlan_offload(uint16_t port_id) dev = &rte_eth_devices[port_id]; dev_offloads = &dev->data->dev_conf.rxmode.offloads; - if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) - ret |= ETH_VLAN_STRIP_OFFLOAD; + if (*dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) + ret |= RTE_ETH_VLAN_STRIP_OFFLOAD; - if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) - ret |= ETH_VLAN_FILTER_OFFLOAD; + if (*dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) + ret |= RTE_ETH_VLAN_FILTER_OFFLOAD; - if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) - ret |= ETH_VLAN_EXTEND_OFFLOAD; + if (*dev_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) + ret |= RTE_ETH_VLAN_EXTEND_OFFLOAD; - if (*dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP) - ret |= ETH_QINQ_STRIP_OFFLOAD; + if (*dev_offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) + ret |= RTE_ETH_QINQ_STRIP_OFFLOAD; return ret; } @@ -4001,7 +4021,7 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, return -EINVAL; } - if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) { + if (pfc_conf->priority > (RTE_ETH_DCB_NUM_USER_PRIORITIES - 1)) { RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n"); return -EINVAL; } @@ -4013,13 +4033,156 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, return -ENOTSUP; } +static int +validate_rx_pause_config(struct rte_eth_dev_info *dev_info, uint8_t tc_max, + struct rte_eth_pfc_queue_conf *pfc_queue_conf) +{ + if ((pfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) || + (pfc_queue_conf->mode == RTE_ETH_FC_FULL)) { + if (pfc_queue_conf->rx_pause.tx_qid >= dev_info->nb_tx_queues) { + RTE_ETHDEV_LOG(ERR, + "PFC Tx queue not in range for Rx pause requested:%d configured:%d\n", + pfc_queue_conf->rx_pause.tx_qid, + dev_info->nb_tx_queues); + return -EINVAL; + } + + if (pfc_queue_conf->rx_pause.tc >= tc_max) { + RTE_ETHDEV_LOG(ERR, + "PFC TC not in range for Rx pause requested:%d max:%d\n", + pfc_queue_conf->rx_pause.tc, tc_max); + return -EINVAL; + } + } + + return 0; +} + +static int +validate_tx_pause_config(struct rte_eth_dev_info *dev_info, uint8_t tc_max, + struct rte_eth_pfc_queue_conf *pfc_queue_conf) +{ + if ((pfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) || + (pfc_queue_conf->mode == RTE_ETH_FC_FULL)) { + if (pfc_queue_conf->tx_pause.rx_qid >= dev_info->nb_rx_queues) { + RTE_ETHDEV_LOG(ERR, + "PFC Rx queue not in range for Tx pause requested:%d configured:%d\n", + pfc_queue_conf->tx_pause.rx_qid, + dev_info->nb_rx_queues); + return -EINVAL; + } + + if (pfc_queue_conf->tx_pause.tc >= tc_max) { + RTE_ETHDEV_LOG(ERR, + "PFC TC not in range for Tx pause requested:%d max:%d\n", + pfc_queue_conf->tx_pause.tc, tc_max); + return -EINVAL; + } + } + + return 0; +} + +int +rte_eth_dev_priority_flow_ctrl_queue_info_get(uint16_t port_id, + struct rte_eth_pfc_queue_info *pfc_queue_info) +{ + struct rte_eth_dev *dev; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + dev = &rte_eth_devices[port_id]; + + if (pfc_queue_info == NULL) { + RTE_ETHDEV_LOG(ERR, "PFC info param is NULL for port (%u)\n", + port_id); + return -EINVAL; + } + + if (*dev->dev_ops->priority_flow_ctrl_queue_info_get) + return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_info_get) + (dev, pfc_queue_info)); + return -ENOTSUP; +} + +int +rte_eth_dev_priority_flow_ctrl_queue_configure(uint16_t port_id, + struct rte_eth_pfc_queue_conf *pfc_queue_conf) +{ + struct rte_eth_pfc_queue_info pfc_info; + struct rte_eth_dev_info dev_info; + struct rte_eth_dev *dev; + int ret; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + dev = &rte_eth_devices[port_id]; + + if (pfc_queue_conf == NULL) { + RTE_ETHDEV_LOG(ERR, "PFC parameters are NULL for port (%u)\n", + port_id); + return -EINVAL; + } + + ret = rte_eth_dev_info_get(port_id, &dev_info); + if (ret != 0) + return ret; + + ret = rte_eth_dev_priority_flow_ctrl_queue_info_get(port_id, &pfc_info); + if (ret != 0) + return ret; + + if (pfc_info.tc_max == 0) { + RTE_ETHDEV_LOG(ERR, "Ethdev port %u does not support PFC TC values\n", + port_id); + return -ENOTSUP; + } + + /* Check requested mode supported or not */ + if (pfc_info.mode_capa == RTE_ETH_FC_RX_PAUSE && + pfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) { + RTE_ETHDEV_LOG(ERR, "PFC Tx pause unsupported for port (%d)\n", + port_id); + return -EINVAL; + } + + if (pfc_info.mode_capa == RTE_ETH_FC_TX_PAUSE && + pfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) { + RTE_ETHDEV_LOG(ERR, "PFC Rx pause unsupported for port (%d)\n", + port_id); + return -EINVAL; + } + + /* Validate Rx pause parameters */ + if (pfc_info.mode_capa == RTE_ETH_FC_FULL || + pfc_info.mode_capa == RTE_ETH_FC_RX_PAUSE) { + ret = validate_rx_pause_config(&dev_info, pfc_info.tc_max, + pfc_queue_conf); + if (ret != 0) + return ret; + } + + /* Validate Tx pause parameters */ + if (pfc_info.mode_capa == RTE_ETH_FC_FULL || + pfc_info.mode_capa == RTE_ETH_FC_TX_PAUSE) { + ret = validate_tx_pause_config(&dev_info, pfc_info.tc_max, + pfc_queue_conf); + if (ret != 0) + return ret; + } + + if (*dev->dev_ops->priority_flow_ctrl_queue_config) + return eth_err(port_id, + (*dev->dev_ops->priority_flow_ctrl_queue_config)( + dev, pfc_queue_conf)); + return -ENOTSUP; +} + static int eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size) { uint16_t i, num; - num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE; + num = (reta_size + RTE_ETH_RETA_GROUP_SIZE - 1) / RTE_ETH_RETA_GROUP_SIZE; for (i = 0; i < num; i++) { if (reta_conf[i].mask) return 0; @@ -4041,8 +4204,8 @@ eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf, } for (i = 0; i < reta_size; i++) { - idx = i / RTE_RETA_GROUP_SIZE; - shift = i % RTE_RETA_GROUP_SIZE; + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; if ((reta_conf[idx].mask & RTE_BIT64(shift)) && (reta_conf[idx].reta[shift] >= max_rxq)) { RTE_ETHDEV_LOG(ERR, @@ -4198,7 +4361,7 @@ rte_eth_dev_udp_tunnel_port_add(uint16_t port_id, return -EINVAL; } - if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { + if (udp_tunnel->prot_type >= RTE_ETH_TUNNEL_TYPE_MAX) { RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); return -EINVAL; } @@ -4224,7 +4387,7 @@ rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, return -EINVAL; } - if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { + if (udp_tunnel->prot_type >= RTE_ETH_TUNNEL_TYPE_MAX) { RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); return -EINVAL; } @@ -4365,8 +4528,8 @@ rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr, port_id); return -EINVAL; } - if (pool >= ETH_64_POOLS) { - RTE_ETHDEV_LOG(ERR, "Pool ID must be 0-%d\n", ETH_64_POOLS - 1); + if (pool >= RTE_ETH_64_POOLS) { + RTE_ETHDEV_LOG(ERR, "Pool ID must be 0-%d\n", RTE_ETH_64_POOLS - 1); return -EINVAL; } @@ -4815,13 +4978,13 @@ rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data) } intr_handle = dev->intr_handle; - if (!intr_handle->intr_vec) { + if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) { RTE_ETHDEV_LOG(ERR, "Rx Intr vector unset\n"); return -EPERM; } for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { - vec = intr_handle->intr_vec[qid]; + vec = rte_intr_vec_list_index_get(intr_handle, qid); rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); if (rc && rc != -EEXIST) { RTE_ETHDEV_LOG(ERR, @@ -4856,15 +5019,15 @@ rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id) } intr_handle = dev->intr_handle; - if (!intr_handle->intr_vec) { + if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) { RTE_ETHDEV_LOG(ERR, "Rx Intr vector unset\n"); return -1; } - vec = intr_handle->intr_vec[queue_id]; + vec = rte_intr_vec_list_index_get(intr_handle, queue_id); efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ? (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec; - fd = intr_handle->efds[efd_idx]; + fd = rte_intr_efds_index_get(intr_handle, efd_idx); return fd; } @@ -5042,12 +5205,12 @@ rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id, } intr_handle = dev->intr_handle; - if (!intr_handle->intr_vec) { + if (rte_intr_vec_list_index_get(intr_handle, 0) < 0) { RTE_ETHDEV_LOG(ERR, "Rx Intr vector unset\n"); return -EPERM; } - vec = intr_handle->intr_vec[queue_id]; + vec = rte_intr_vec_list_index_get(intr_handle, queue_id); rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); if (rc && rc != -EEXIST) { RTE_ETHDEV_LOG(ERR, @@ -6275,7 +6438,7 @@ eth_dev_handle_port_link_status(const char *cmd __rte_unused, rte_tel_data_add_dict_string(d, status_str, "UP"); rte_tel_data_add_dict_u64(d, "speed", link.link_speed); rte_tel_data_add_dict_string(d, "duplex", - (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? + (link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? "full-duplex" : "half-duplex"); return 0; } @@ -6311,8 +6474,10 @@ eth_dev_handle_port_info(const char *cmd __rte_unused, return -ENOMEM; txq_state = rte_tel_data_alloc(); - if (!txq_state) + if (!txq_state) { + rte_tel_data_free(rxq_state); return -ENOMEM; + } rte_tel_data_start_dict(d); rte_tel_data_add_dict_string(d, "name", eth_dev->data->name);