X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_acl%2Frte_acl_osdep_alone.h;h=a84b6f970b9ee47823a5b8ad1f3fd78df4afab07;hb=fdf20fa7bee9df9037116318a87080e1eb7e757e;hp=a7b7424d68efb47aa9df1a931dcab3149a14d88f;hpb=6f41fe75e2dd8dd38f7bea7b9501edd4f9b72fa5;p=dpdk.git

diff --git a/lib/librte_acl/rte_acl_osdep_alone.h b/lib/librte_acl/rte_acl_osdep_alone.h
index a7b7424d68..a84b6f970b 100644
--- a/lib/librte_acl/rte_acl_osdep_alone.h
+++ b/lib/librte_acl/rte_acl_osdep_alone.h
@@ -104,7 +104,7 @@ extern "C" {
  * Searches the input parameter for the least significant set bit
  * (starting from zero).
  * If a least significant 1 bit is found, its bit index is returned.
- * If the content of the input paramer is zero, then the content of the return
+ * If the content of the input parameter is zero, then the content of the return
  * value is undefined.
  * @param v
  *     input parameter, should not be zero.
@@ -180,13 +180,13 @@ rte_rdtsc(void)
  * rte_memory related.
  */
 #define	SOCKET_ID_ANY	-1                  /**< Any NUMA socket. */
-#define	CACHE_LINE_SIZE	64                  /**< Cache line size. */
-#define	CACHE_LINE_MASK	(CACHE_LINE_SIZE-1) /**< Cache line mask. */
+#define	RTE_CACHE_LINE_SIZE	64                  /**< Cache line size. */
+#define	RTE_CACHE_LINE_MASK	(RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */
 
 /**
  * Force alignment to cache line.
  */
-#define	__rte_cache_aligned	__attribute__((__aligned__(CACHE_LINE_SIZE)))
+#define	__rte_cache_aligned	__attribute__((__aligned__(RTE_CACHE_LINE_SIZE)))
 
 
 /*