X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_eal%2Fcommon%2Finclude%2Farch%2Farm%2Frte_atomic_32.h;h=7dc0d06d14aec70f22801aeb19f173a225f0609b;hb=3a1a885e036c78521f74fdf7777f24e9dc3466df;hp=859562e593228a72f14ddd58b4132fb1fb888f9b;hpb=8015c5593acc3ed490d75c70ff67961b7e278e38;p=dpdk.git

diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
index 859562e593..7dc0d06d14 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
@@ -15,28 +15,10 @@ extern "C" {
 
 #include "generic/rte_atomic.h"
 
-/**
- * General memory barrier.
- *
- * Guarantees that the LOAD and STORE operations generated before the
- * barrier occur before the LOAD and STORE operations generated after.
- */
 #define	rte_mb()  __sync_synchronize()
 
-/**
- * Write memory barrier.
- *
- * Guarantees that the STORE operations generated before the barrier
- * occur before the STORE operations generated after.
- */
 #define	rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while (0)
 
-/**
- * Read memory barrier.
- *
- * Guarantees that the LOAD operations generated before the barrier
- * occur before the LOAD operations generated after.
- */
 #define	rte_rmb() __sync_synchronize()
 
 #define rte_smp_mb() rte_mb()