X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_eal%2Flinuxapp%2Figb_uio%2Fcompat.h;h=0d781e482562703d640fc70ef76089f1592f77c6;hb=de9b91e8576f21774ce103d295dc56877d3e3fa7;hp=676fa1b385d59de7c8d3d215432c225f64c1f19e;hpb=11ba04265cfd2a53c12c030fcaa5dfe7eed39a42;p=dpdk.git

diff --git a/lib/librte_eal/linuxapp/igb_uio/compat.h b/lib/librte_eal/linuxapp/igb_uio/compat.h
index 676fa1b385..0d781e4825 100644
--- a/lib/librte_eal/linuxapp/igb_uio/compat.h
+++ b/lib/librte_eal/linuxapp/igb_uio/compat.h
@@ -11,6 +11,10 @@
 #define pci_cfg_access_unlock pci_unblock_user_cfg_access
 #endif
 
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
+#define HAVE_PTE_MASK_PAGE_IOMAP
+#endif
+
 #ifndef PCI_MSIX_ENTRY_SIZE
 #define PCI_MSIX_ENTRY_SIZE             16
 #define  PCI_MSIX_ENTRY_LOWER_ADDR      0
@@ -20,8 +24,18 @@
 #define   PCI_MSIX_ENTRY_CTRL_MASKBIT   1
 #endif
 
+/*
+ * for kernels < 2.6.38 and backported patch that moves MSI-X entry definition
+ * to pci_regs.h Those kernels has PCI_MSIX_ENTRY_SIZE defined but not
+ * PCI_MSIX_ENTRY_CTRL_MASKBIT
+ */
+#ifndef PCI_MSIX_ENTRY_CTRL_MASKBIT
+#define PCI_MSIX_ENTRY_CTRL_MASKBIT    1
+#endif
+
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34) && \
-	!defined(CONFIG_PCI_IOV)
+	(!(defined(RHEL_RELEASE_CODE) && \
+	 RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 9)))
 
 static int pci_num_vf(struct pci_dev *dev)
 {
@@ -43,6 +57,14 @@ static int pci_num_vf(struct pci_dev *dev)
 
 #endif /* < 2.6.34 */
 
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && \
+	(!(defined(RHEL_RELEASE_CODE) && \
+	   RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))
+
+#define kstrtoul strict_strtoul
+
+#endif /* < 2.6.39 */
+
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0) && \
 	(!(defined(RHEL_RELEASE_CODE) && \
 	   RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)))