X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_eal%2Flinuxapp%2Figb_uio%2Figb_uio.c;h=41bf6ea39a0985762868c95a2121a40eae62a16e;hb=f0d1896fa14385dc9b16065594012cdc8a449ee1;hp=51733f6822f60ec9a5c24207e853e8ea570c29d6;hpb=af75078fece3615088e561357c1e97603e43a5fe;p=dpdk.git diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c index 51733f6822..41bf6ea39a 100644 --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c @@ -1,25 +1,29 @@ /*- + * GPL LICENSE SUMMARY * - * Copyright (c) 2010-2012, Intel Corporation + * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * GNU GPL V2: http://www.gnu.org/licenses/old-licenses/gpl-2.0.html + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. * + * Contact Information: + * Intel Corporation */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include #include #include @@ -27,38 +31,14 @@ #include #include #include +#include -/* Some function names changes between 3.2.0 and 3.3.0... */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -#define PCI_LOCK pci_block_user_cfg_access -#define PCI_UNLOCK pci_unblock_user_cfg_access -#else -#define PCI_LOCK pci_cfg_access_lock -#define PCI_UNLOCK pci_cfg_access_unlock +#ifdef CONFIG_XEN_DOM0 +#include #endif +#include -/** - * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39, - * but none of them in kernel 2.6.35. - */ -#ifndef PCI_MSIX_ENTRY_SIZE -#define PCI_MSIX_ENTRY_SIZE 16 -#define PCI_MSIX_ENTRY_LOWER_ADDR 0 -#define PCI_MSIX_ENTRY_UPPER_ADDR 4 -#define PCI_MSIX_ENTRY_DATA 8 -#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 -#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 -#endif - -#define IGBUIO_NUM_MSI_VECTORS 1 - -/* interrupt mode */ -enum igbuio_intr_mode { - IGBUIO_LEGACY_INTR_MODE = 0, - IGBUIO_MSI_INTR_MODE, - IGBUIO_MSIX_INTR_MODE, - IGBUIO_INTR_MODE_MAX -}; +#include "compat.h" /** * A structure describing the private information for a uio device. @@ -66,34 +46,58 @@ enum igbuio_intr_mode { struct rte_uio_pci_dev { struct uio_info info; struct pci_dev *pdev; - spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */ - enum igbuio_intr_mode mode; - struct msix_entry \ - msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */ + enum rte_intr_mode mode; }; -static const enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE; +static char *intr_mode; +static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX; -/* PCI device id table */ -static struct pci_device_id igbuio_pci_ids[] = { -#define RTE_PCI_DEV_ID_DECL(vend, dev) {PCI_DEVICE(vend, dev)}, -#include -{ 0, }, -}; +/* sriov sysfs */ +static ssize_t +show_max_vfs(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, 10, "%u\n", dev_num_vf(dev)); +} -static inline struct rte_uio_pci_dev * -igbuio_get_uio_pci_dev(struct uio_info *info) +static ssize_t +store_max_vfs(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) { - return container_of(info, struct rte_uio_pci_dev, info); + int err = 0; + unsigned long max_vfs; + struct pci_dev *pdev = to_pci_dev(dev); + + if (0 != kstrtoul(buf, 0, &max_vfs)) + return -EINVAL; + + if (0 == max_vfs) + pci_disable_sriov(pdev); + else if (0 == pci_num_vf(pdev)) + err = pci_enable_sriov(pdev, max_vfs); + else /* do nothing if change max_vfs number */ + err = -EINVAL; + + return err ? err : count; } -/** +static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs); + +static struct attribute *dev_attrs[] = { + &dev_attr_max_vfs.attr, + NULL, +}; + +static const struct attribute_group dev_attr_grp = { + .attrs = dev_attrs, +}; +/* * It masks the msix on/off of generating MSI-X messages. */ -static int +static void igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state) { - uint32_t mask_bits = desc->masked; + u32 mask_bits = desc->masked; unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; @@ -107,49 +111,6 @@ igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state) readl(desc->mask_base); desc->masked = mask_bits; } - - return 0; -} - -/** - * This function sets/clears the masks for generating LSC interrupts. - * - * @param info - * The pointer to struct uio_info. - * @param on - * The on/off flag of masking LSC. - * @return - * -On success, zero value. - * -On failure, a negative value. - */ -static int -igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state) -{ - struct pci_dev *pdev = udev->pdev; - - if (udev->mode == IGBUIO_MSIX_INTR_MODE) { - struct msi_desc *desc; - - list_for_each_entry(desc, &pdev->msi_list, list) { - igbuio_msix_mask_irq(desc, state); - } - } - else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) { - uint32_t status; - uint16_t old, new; - - pci_read_config_dword(pdev, PCI_COMMAND, &status); - old = status; - if (state != 0) - new = old & (~PCI_COMMAND_INTX_DISABLE); - else - new = old | PCI_COMMAND_INTX_DISABLE; - - if (old != new) - pci_write_config_word(pdev, PCI_COMMAND, new); - } - - return 0; } /** @@ -168,17 +129,25 @@ igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state) static int igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state) { - unsigned long flags; - struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info); + struct rte_uio_pci_dev *udev = info->priv; struct pci_dev *pdev = udev->pdev; - spin_lock_irqsave(&udev->lock, flags); - PCI_LOCK(pdev); + pci_cfg_access_lock(pdev); + if (udev->mode == RTE_INTR_MODE_LEGACY) + pci_intx(pdev, !!irq_state); - igbuio_set_interrupt_mask(udev, irq_state); + else if (udev->mode == RTE_INTR_MODE_MSIX) { + struct msi_desc *desc; - PCI_UNLOCK(pdev); - spin_unlock_irqrestore(&udev->lock, flags); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)) + list_for_each_entry(desc, &pdev->msi_list, list) + igbuio_msix_mask_irq(desc, irq_state); +#else + list_for_each_entry(desc, &pdev->dev.msi_list, list) + igbuio_msix_mask_irq(desc, irq_state); +#endif + } + pci_cfg_access_unlock(pdev); return 0; } @@ -190,37 +159,63 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state) static irqreturn_t igbuio_pci_irqhandler(int irq, struct uio_info *info) { - irqreturn_t ret = IRQ_NONE; - unsigned long flags; - struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info); - struct pci_dev *pdev = udev->pdev; - uint32_t cmd_status_dword; - uint16_t status; - - spin_lock_irqsave(&udev->lock, flags); - /* block userspace PCI config reads/writes */ - PCI_LOCK(pdev); - - /* for legacy mode, interrupt maybe shared */ - if (udev->mode == IGBUIO_LEGACY_INTR_MODE) { - pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword); - status = cmd_status_dword >> 16; - /* interrupt is not ours, goes to out */ - if (!(status & PCI_STATUS_INTERRUPT)) - goto done; - } + struct rte_uio_pci_dev *udev = info->priv; - igbuio_set_interrupt_mask(udev, 0); - ret = IRQ_HANDLED; -done: - /* unblock userspace PCI config reads/writes */ - PCI_UNLOCK(pdev); - spin_unlock_irqrestore(&udev->lock, flags); - printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled"); + /* Legacy mode need to mask in hardware */ + if (udev->mode == RTE_INTR_MODE_LEGACY && + !pci_check_and_mask_intx(udev->pdev)) + return IRQ_NONE; - return ret; + /* Message signal mode, no share IRQ and automasked */ + return IRQ_HANDLED; } +#ifdef CONFIG_XEN_DOM0 +static int +igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma) +{ + int idx; + + idx = (int)vma->vm_pgoff; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); +#ifdef HAVE_PTE_MASK_PAGE_IOMAP + vma->vm_page_prot.pgprot |= _PAGE_IOMAP; +#endif + + return remap_pfn_range(vma, + vma->vm_start, + info->mem[idx].addr >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot); +} + +/** + * This is uio device mmap method which will use igbuio mmap for Xen + * Dom0 environment. + */ +static int +igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma) +{ + int idx; + + if (vma->vm_pgoff >= MAX_UIO_MAPS) + return -EINVAL; + + if (info->mem[vma->vm_pgoff].size == 0) + return -EINVAL; + + idx = (int)vma->vm_pgoff; + switch (info->mem[idx].memtype) { + case UIO_MEM_PHYS: + return igbuio_dom0_mmap_phys(info, vma); + case UIO_MEM_LOGICAL: + case UIO_MEM_VIRTUAL: + default: + return -EINVAL; + } +} +#endif + /* Remap pci resources described by bar #pci_bar in uio resource n. */ static int igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info, @@ -229,6 +224,9 @@ igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info, unsigned long addr, len; void *internal_addr; + if (n >= ARRAY_SIZE(info->mem)) + return -EINVAL; + addr = pci_resource_start(dev, pci_bar); len = pci_resource_len(dev, pci_bar); if (addr == 0 || len == 0) @@ -244,21 +242,93 @@ igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info, return 0; } +/* Get pci port io resources described by bar #pci_bar in uio resource n. */ +static int +igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info, + int n, int pci_bar, const char *name) +{ + unsigned long addr, len; + + if (n >= ARRAY_SIZE(info->port)) + return -EINVAL; + + addr = pci_resource_start(dev, pci_bar); + len = pci_resource_len(dev, pci_bar); + if (addr == 0 || len == 0) + return -EINVAL; + + info->port[n].name = name; + info->port[n].start = addr; + info->port[n].size = len; + info->port[n].porttype = UIO_PORT_X86; + + return 0; +} + /* Unmap previously ioremap'd resources */ static void igbuio_pci_release_iomem(struct uio_info *info) { int i; + for (i = 0; i < MAX_UIO_MAPS; i++) { if (info->mem[i].internal_addr) iounmap(info->mem[i].internal_addr); } } +static int +igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info) +{ + int i, iom, iop, ret; + unsigned long flags; + static const char *bar_names[PCI_STD_RESOURCE_END + 1] = { + "BAR0", + "BAR1", + "BAR2", + "BAR3", + "BAR4", + "BAR5", + }; + + iom = 0; + iop = 0; + + for (i = 0; i < ARRAY_SIZE(bar_names); i++) { + if (pci_resource_len(dev, i) != 0 && + pci_resource_start(dev, i) != 0) { + flags = pci_resource_flags(dev, i); + if (flags & IORESOURCE_MEM) { + ret = igbuio_pci_setup_iomem(dev, info, iom, + i, bar_names[i]); + if (ret != 0) + return ret; + iom++; + } else if (flags & IORESOURCE_IO) { + ret = igbuio_pci_setup_ioport(dev, info, iop, + i, bar_names[i]); + if (ret != 0) + return ret; + iop++; + } + } + } + + return (iom != 0 || iop != 0) ? ret : -ENOENT; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0) static int __devinit +#else +static int +#endif igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) { struct rte_uio_pci_dev *udev; + struct msix_entry msix_entry; + dma_addr_t map_dma_addr; + void *map_addr; + int err; udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL); if (!udev) @@ -268,116 +338,168 @@ igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) * enable device: ask low-level code to enable I/O and * memory */ - if (pci_enable_device(dev)) { - printk(KERN_ERR "Cannot enable PCI device\n"); + err = pci_enable_device(dev); + if (err != 0) { + dev_err(&dev->dev, "Cannot enable PCI device\n"); goto fail_free; } - /* XXX should we use 64 bits ? */ - /* set 32-bit DMA mask */ - if (pci_set_dma_mask(dev,(uint64_t)0xffffffff)) { - printk(KERN_ERR "Cannot set DMA mask\n"); - goto fail_disable; - } - - /* - * reserve device's PCI memory regions for use by this - * module - */ - if (pci_request_regions(dev, "igb_uio")) { - printk(KERN_ERR "Cannot request regions\n"); - goto fail_disable; - } - /* enable bus mastering on the device */ pci_set_master(dev); /* remap IO memory */ - if (igbuio_pci_setup_iomem(dev, &udev->info, 0, 0, "config")) - goto fail_release_regions; + err = igbuio_setup_bars(dev, &udev->info); + if (err != 0) + goto fail_release_iomem; + + /* set 64-bit DMA mask */ + err = pci_set_dma_mask(dev, DMA_BIT_MASK(64)); + if (err != 0) { + dev_err(&dev->dev, "Cannot set DMA mask\n"); + goto fail_release_iomem; + } + + err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64)); + if (err != 0) { + dev_err(&dev->dev, "Cannot set consistent DMA mask\n"); + goto fail_release_iomem; + } /* fill uio infos */ - udev->info.name = "Intel IGB UIO"; + udev->info.name = "igb_uio"; udev->info.version = "0.1"; udev->info.handler = igbuio_pci_irqhandler; udev->info.irqcontrol = igbuio_pci_irqcontrol; +#ifdef CONFIG_XEN_DOM0 + /* check if the driver run on Xen Dom0 */ + if (xen_initial_domain()) + udev->info.mmap = igbuio_dom0_pci_mmap; +#endif udev->info.priv = udev; udev->pdev = dev; - udev->mode = 0; /* set the default value for interrupt mode */ - spin_lock_init(&udev->lock); - - /* check if it need to try msix first */ - if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) { - int vector; - for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++) - udev->msix_entries[vector].entry = vector; - - if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) { - udev->mode = IGBUIO_MSIX_INTR_MODE; + switch (igbuio_intr_mode_preferred) { + case RTE_INTR_MODE_MSIX: + /* Only 1 msi-x vector needed */ + msix_entry.entry = 0; + if (pci_enable_msix(dev, &msix_entry, 1) == 0) { + dev_dbg(&dev->dev, "using MSI-X"); + udev->info.irq_flags = IRQF_NO_THREAD; + udev->info.irq = msix_entry.vector; + udev->mode = RTE_INTR_MODE_MSIX; + break; } - else { - pci_disable_msix(udev->pdev); - printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n"); + /* fall back to INTX */ + case RTE_INTR_MODE_LEGACY: + if (pci_intx_mask_supported(dev)) { + dev_dbg(&dev->dev, "using INTX"); + udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD; + udev->info.irq = dev->irq; + udev->mode = RTE_INTR_MODE_LEGACY; + break; } - } - switch (udev->mode) { - case IGBUIO_MSIX_INTR_MODE: - udev->info.irq_flags = 0; - udev->info.irq = udev->msix_entries[0].vector; - break; - case IGBUIO_MSI_INTR_MODE: - break; - case IGBUIO_LEGACY_INTR_MODE: - udev->info.irq_flags = IRQF_SHARED; - udev->info.irq = dev->irq; + dev_notice(&dev->dev, "PCI INTX mask not supported\n"); + /* fall back to no IRQ */ + case RTE_INTR_MODE_NONE: + udev->mode = RTE_INTR_MODE_NONE; + udev->info.irq = 0; break; + default: - break; + dev_err(&dev->dev, "invalid IRQ mode %u", + igbuio_intr_mode_preferred); + err = -EINVAL; + goto fail_release_iomem; } - pci_set_drvdata(dev, udev); - igbuio_pci_irqcontrol(&udev->info, 0); + err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp); + if (err != 0) + goto fail_release_iomem; /* register uio driver */ - if (uio_register_device(&dev->dev, &udev->info)) - goto fail_release_iomem; + err = uio_register_device(&dev->dev, &udev->info); + if (err != 0) + goto fail_remove_group; + + pci_set_drvdata(dev, udev); - printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq); + dev_info(&dev->dev, "uio device registered with irq %lx\n", + udev->info.irq); + + /* + * Doing a harmless dma mapping for attaching the device to + * the iommu identity mapping if kernel boots with iommu=pt. + * Note this is not a problem if no IOMMU at all. + */ + map_addr = dma_zalloc_coherent(&dev->dev, 1024, + &map_dma_addr, GFP_KERNEL); + + if (!map_addr) + dev_info(&dev->dev, "dma mapping failed\n"); + else { + dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n", + (unsigned long long)map_dma_addr, map_addr); + + dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr); + dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n", + (unsigned long long)map_dma_addr, map_addr); + } return 0; +fail_remove_group: + sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp); fail_release_iomem: igbuio_pci_release_iomem(&udev->info); - if (udev->mode == IGBUIO_MSIX_INTR_MODE) + if (udev->mode == RTE_INTR_MODE_MSIX) pci_disable_msix(udev->pdev); -fail_release_regions: - pci_release_regions(dev); -fail_disable: pci_disable_device(dev); fail_free: kfree(udev); - return -ENODEV; + return err; } static void igbuio_pci_remove(struct pci_dev *dev) { - struct uio_info *info = pci_get_drvdata(dev); + struct rte_uio_pci_dev *udev = pci_get_drvdata(dev); - uio_unregister_device(info); - if (((struct rte_uio_pci_dev *)info->priv)->mode == IGBUIO_MSIX_INTR_MODE) + sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp); + uio_unregister_device(&udev->info); + igbuio_pci_release_iomem(&udev->info); + if (udev->mode == RTE_INTR_MODE_MSIX) pci_disable_msix(dev); - pci_release_regions(dev); pci_disable_device(dev); pci_set_drvdata(dev, NULL); - kfree(info); + kfree(udev); +} + +static int +igbuio_config_intr_mode(char *intr_str) +{ + if (!intr_str) { + pr_info("Use MSIX interrupt by default\n"); + return 0; + } + + if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) { + igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX; + pr_info("Use MSIX interrupt\n"); + } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) { + igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY; + pr_info("Use legacy interrupt\n"); + } else { + pr_info("Error: bad parameter - %s\n", intr_str); + return -EINVAL; + } + + return 0; } static struct pci_driver igbuio_pci_driver = { .name = "igb_uio", - .id_table = igbuio_pci_ids, + .id_table = NULL, .probe = igbuio_pci_probe, .remove = igbuio_pci_remove, }; @@ -385,6 +507,12 @@ static struct pci_driver igbuio_pci_driver = { static int __init igbuio_pci_init_module(void) { + int ret; + + ret = igbuio_config_intr_mode(intr_mode); + if (ret < 0) + return ret; + return pci_register_driver(&igbuio_pci_driver); } @@ -397,6 +525,13 @@ igbuio_pci_exit_module(void) module_init(igbuio_pci_init_module); module_exit(igbuio_pci_exit_module); +module_param(intr_mode, charp, S_IRUGO); +MODULE_PARM_DESC(intr_mode, +"igb_uio interrupt mode (default=msix):\n" +" " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n" +" " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n" +"\n"); + MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards"); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Intel Corporation");