X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_ether%2Frte_eth_ctrl.h;h=f71669c3a6f60be75ff2116ba74da178ea7ddf54;hb=492d31ac02a3df8ff843b7153b4f780af03bf002;hp=b2348141e1d4d0ec3d976240be719a387be67215;hpb=38eef41d6ce7a8f9519d4e678bf9e494c6bca3d5;p=dpdk.git diff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h index b2348141e1..f71669c3a6 100644 --- a/lib/librte_ether/rte_eth_ctrl.h +++ b/lib/librte_ether/rte_eth_ctrl.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -46,6 +46,36 @@ extern "C" { #endif +/* + * A packet can be identified by hardware as different flow types. Different + * NIC hardwares may support different flow types. + * Basically, the NIC hardware identifies the flow type as deep protocol as + * possible, and exclusively. For example, if a packet is identified as + * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types, + * though it is an actual IPV4 packet. + * Note that the flow types are used to define RSS offload types in + * rte_ethdev.h. + */ +#define RTE_ETH_FLOW_UNKNOWN 0 +#define RTE_ETH_FLOW_RAW 1 +#define RTE_ETH_FLOW_IPV4 2 +#define RTE_ETH_FLOW_FRAG_IPV4 3 +#define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4 +#define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5 +#define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6 +#define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7 +#define RTE_ETH_FLOW_IPV6 8 +#define RTE_ETH_FLOW_FRAG_IPV6 9 +#define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10 +#define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11 +#define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12 +#define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13 +#define RTE_ETH_FLOW_L2_PAYLOAD 14 +#define RTE_ETH_FLOW_IPV6_EX 15 +#define RTE_ETH_FLOW_IPV6_TCP_EX 16 +#define RTE_ETH_FLOW_IPV6_UDP_EX 17 +#define RTE_ETH_FLOW_MAX 18 + /** * Feature filter types */ @@ -79,7 +109,7 @@ enum rte_filter_op { RTE_ETH_FILTER_OP_MAX }; -/* +/** * MAC filter type */ enum rte_mac_filter_type { @@ -265,25 +295,110 @@ struct rte_eth_tunnel_filter_conf { uint16_t queue_id; /** < queue number. */ }; -#define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */ +/** + * Global eth device configuration type. + */ +enum rte_eth_global_cfg_type { + RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0, + RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN, + RTE_ETH_GLOBAL_CFG_TYPE_MAX, +}; + +/** + * Global eth device configuration. + */ +struct rte_eth_global_cfg { + enum rte_eth_global_cfg_type cfg_type; /**< Global config type. */ + union { + uint8_t gre_key_len; /**< Valid GRE key length in byte. */ + uint64_t reserved; /**< Reserve space for future use. */ + } cfg; +}; + +#define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */ +#define RTE_ETH_INSET_SIZE_MAX 128 /** < Max length of input set. */ + +/** + * Input set fields for Flow Director and Hash filters + */ +enum rte_eth_input_set_field { + RTE_ETH_INPUT_SET_UNKNOWN = 0, + + /* L2 */ + RTE_ETH_INPUT_SET_L2_SRC_MAC = 1, + RTE_ETH_INPUT_SET_L2_DST_MAC, + RTE_ETH_INPUT_SET_L2_OUTER_VLAN, + RTE_ETH_INPUT_SET_L2_INNER_VLAN, + RTE_ETH_INPUT_SET_L2_ETHERTYPE, + + /* L3 */ + RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129, + RTE_ETH_INPUT_SET_L3_DST_IP4, + RTE_ETH_INPUT_SET_L3_SRC_IP6, + RTE_ETH_INPUT_SET_L3_DST_IP6, + RTE_ETH_INPUT_SET_L3_IP4_TOS, + RTE_ETH_INPUT_SET_L3_IP4_PROTO, + RTE_ETH_INPUT_SET_L3_IP6_TC, + RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER, + + /* L4 */ + RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257, + RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, + RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, + RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, + RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, + RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, + RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG, + + /* Tunnel */ + RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385, + RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC, + RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN, + RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, + RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, + + /* Flexible Payload */ + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD, + RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD, + + RTE_ETH_INPUT_SET_DEFAULT = 65533, + RTE_ETH_INPUT_SET_NONE = 65534, + RTE_ETH_INPUT_SET_MAX = 65535, +}; + +/** + * Filters input set operations + */ +enum rte_filter_input_set_op { + RTE_ETH_INPUT_SET_OP_UNKNOWN, + RTE_ETH_INPUT_SET_SELECT, /**< select input set */ + RTE_ETH_INPUT_SET_ADD, /**< add input set entry */ + RTE_ETH_INPUT_SET_OP_MAX +}; + + +/** + * A structure used to define the input set configuration for + * flow director and hash filters + */ +struct rte_eth_input_set_conf { + uint16_t flow_type; + uint16_t inset_size; + enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX]; + enum rte_filter_input_set_op op; +}; /** - * Flow type + * A structure used to define the input for L2 flow */ -enum rte_eth_flow_type { - RTE_ETH_FLOW_TYPE_NONE = 0, - RTE_ETH_FLOW_TYPE_RAW, - RTE_ETH_FLOW_TYPE_UDPV4, - RTE_ETH_FLOW_TYPE_TCPV4, - RTE_ETH_FLOW_TYPE_SCTPV4, - RTE_ETH_FLOW_TYPE_IPV4_OTHER, - RTE_ETH_FLOW_TYPE_FRAG_IPV4, - RTE_ETH_FLOW_TYPE_UDPV6, - RTE_ETH_FLOW_TYPE_TCPV6, - RTE_ETH_FLOW_TYPE_SCTPV6, - RTE_ETH_FLOW_TYPE_IPV6_OTHER, - RTE_ETH_FLOW_TYPE_FRAG_IPV6, - RTE_ETH_FLOW_TYPE_MAX = 64, +struct rte_eth_l2_flow { + uint16_t ether_type; /**< Ether type to match */ }; /** @@ -317,6 +432,8 @@ struct rte_eth_tcpv4_flow { */ struct rte_eth_sctpv4_flow { struct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */ + uint16_t src_port; /**< SCTP source port to match. */ + uint16_t dst_port; /**< SCTP destination port to match. */ uint32_t verify_tag; /**< Verify tag to match */ }; @@ -351,13 +468,42 @@ struct rte_eth_tcpv6_flow { */ struct rte_eth_sctpv6_flow { struct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */ + uint16_t src_port; /**< SCTP source port to match. */ + uint16_t dst_port; /**< SCTP destination port to match. */ uint32_t verify_tag; /**< Verify tag to match */ }; +/** + * A structure used to define the input for MAC VLAN flow + */ +struct rte_eth_mac_vlan_flow { + struct ether_addr mac_addr; /**< Mac address to match. */ +}; + +/** + * Tunnel type for flow director. + */ +enum rte_eth_fdir_tunnel_type { + RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0, + RTE_FDIR_TUNNEL_TYPE_NVGRE, + RTE_FDIR_TUNNEL_TYPE_VXLAN, +}; + +/** + * A structure used to define the input for tunnel flow, now it's VxLAN or + * NVGRE + */ +struct rte_eth_tunnel_flow { + enum rte_eth_fdir_tunnel_type tunnel_type; /**< Tunnel type to match. */ + uint32_t tunnel_id; /**< Tunnel ID to match. TNI, VNI... */ + struct ether_addr mac_addr; /**< Mac address to match. */ +}; + /** * An union contains the inputs for all types of flow */ union rte_eth_fdir_flow { + struct rte_eth_l2_flow l2_flow; struct rte_eth_udpv4_flow udp4_flow; struct rte_eth_tcpv4_flow tcp4_flow; struct rte_eth_sctpv4_flow sctp4_flow; @@ -366,6 +512,8 @@ union rte_eth_fdir_flow { struct rte_eth_tcpv6_flow tcp6_flow; struct rte_eth_sctpv6_flow sctp6_flow; struct rte_eth_ipv6_flow ipv6_flow; + struct rte_eth_mac_vlan_flow mac_vlan_flow; + struct rte_eth_tunnel_flow tunnel_flow; }; /** @@ -381,7 +529,7 @@ struct rte_eth_fdir_flow_ext { * A structure used to define the input for a flow director filter entry */ struct rte_eth_fdir_input { - enum rte_eth_flow_type flow_type; /**< Type of flow */ + uint16_t flow_type; union rte_eth_fdir_flow flow; /**< Flow fields to match, dependent on flow_type */ struct rte_eth_fdir_flow_ext flow_ext; @@ -442,6 +590,9 @@ struct rte_eth_fdir_masks { struct rte_eth_ipv6_flow ipv6_mask; uint16_t src_port_mask; uint16_t dst_port_mask; + uint8_t mac_addr_byte_mask; /** Per byte MAC address mask */ + uint32_t tunnel_id_mask; /** tunnel ID mask */ + uint8_t tunnel_type_mask; }; /** @@ -474,21 +625,21 @@ struct rte_eth_flex_payload_cfg { * for each flow type */ struct rte_eth_fdir_flex_mask { - enum rte_eth_flow_type flow_type; /**< Flow type */ + uint16_t flow_type; uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]; /**< Mask for the whole flexible payload */ }; /** * A structure used to define all flexible payload related setting - * include flexpay load and flex mask + * include flex payload and flex mask */ struct rte_eth_fdir_flex_conf { uint16_t nb_payloads; /**< The number of following payload cfg */ uint16_t nb_flexmasks; /**< The number of following mask */ struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]; /**< Flex payload configuration for each payload type */ - struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_TYPE_MAX]; + struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]; /**< Flex mask configuration for each flow type */ }; @@ -499,8 +650,14 @@ enum rte_fdir_mode { RTE_FDIR_MODE_NONE = 0, /**< Disable FDIR support. */ RTE_FDIR_MODE_SIGNATURE, /**< Enable FDIR signature filter mode. */ RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */ + RTE_FDIR_MODE_PERFECT_MAC_VLAN, /**< Enable FDIR filter mode - MAC VLAN. */ + RTE_FDIR_MODE_PERFECT_TUNNEL, /**< Enable FDIR filter mode - tunnel. */ }; +#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) +#define RTE_FLOW_MASK_ARRAY_SIZE \ + (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) + /** * A structure used to get the information of flow director filter. * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_INFO operation. @@ -516,7 +673,7 @@ struct rte_eth_fdir_info { uint32_t guarant_spc; /**< Guaranteed spaces.*/ uint32_t best_spc; /**< Best effort spaces.*/ /** Bit mask for every supported flow type. */ - uint32_t flow_types_mask[RTE_ETH_FLOW_TYPE_MAX / sizeof(uint32_t)]; + uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]; uint32_t max_flexpayload; /**< Total flex payload in bytes. */ /** Flexible payload unit in bytes. Size and alignments of all flex payload segments should be multiplies of this value. */ @@ -554,6 +711,29 @@ struct rte_eth_fdir_stats { uint32_t best_cnt; /**< Number of filters in best effort spaces. */ }; +/** + * Flow Director filter information types. + */ +enum rte_eth_fdir_filter_info_type { + RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0, + /** Flow Director filter input set configuration */ + RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT, + RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX, +}; + +/** + * A structure used to set FDIR filter information, to support filter type + * of 'RTE_ETH_FILTER_FDIR' RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT operation. + */ +struct rte_eth_fdir_filter_info { + enum rte_eth_fdir_filter_info_type info_type; /**< Information type */ + /** Details of fdir filter information */ + union { + /** Flow Director input set configuration per port */ + struct rte_eth_input_set_conf input_set_conf; + } info; +}; + /** * Hash filter information types. * - RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT is for getting/setting the @@ -561,6 +741,8 @@ struct rte_eth_fdir_stats { * - RTE_ETH_HASH_FILTER_GLOBAL_CONFIG is for getting/setting the global * configurations of hash filters. Those global configurations are valid * for all ports of the same NIC. + * - RTE_ETH_HASH_FILTER_INPUT_SET_SELECT is for setting the global + * hash input set fields */ enum rte_eth_hash_filter_info_type { RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0, @@ -568,6 +750,8 @@ enum rte_eth_hash_filter_info_type { RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT, /** Configure globally for hash filter */ RTE_ETH_HASH_FILTER_GLOBAL_CONFIG, + /** Global Hash filter input set configuration */ + RTE_ETH_HASH_FILTER_INPUT_SET_SELECT, RTE_ETH_HASH_FILTER_INFO_TYPE_MAX, }; @@ -581,14 +765,13 @@ enum rte_eth_hash_function { RTE_ETH_HASH_FUNCTION_MAX, }; -#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ - (RTE_ALIGN(RTE_ETH_FLOW_TYPE_MAX, UINT32_BIT)/UINT32_BIT) + (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) /** * A structure used to set or get global hash function configurations which * include symmetric hash enable per flow type and hash function type. * Each bit in sym_hash_enable_mask[] indicates if the symmetric hash of the - * coresponding flow type is enabled or not. + * corresponding flow type is enabled or not. * Each bit in valid_bit_mask[] indicates if the corresponding bit in * sym_hash_enable_mask[] is valid or not. For the configurations gotten, it * also means if the flow type is supported by hardware or not. @@ -613,6 +796,8 @@ struct rte_eth_hash_filter_info { uint8_t enable; /** Global configurations of hash filter */ struct rte_eth_hash_global_conf global_conf; + /** Global configurations of hash filter input set */ + struct rte_eth_input_set_conf input_set_conf; } info; };