X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_pmd_e1000%2Fe1000%2Fe1000_82571.c;h=8ae1cb12e208765b81394d830609c02313ab6113;hb=afd7f2d86a7e9bfa286224d12e558330b0ef4ed2;hp=bd95bc911f7614a312e750846476a9cb13ff5f99;hpb=5a32a257f957fd88623d5cf9a0873d996f889ca6;p=dpdk.git diff --git a/lib/librte_pmd_e1000/e1000/e1000_82571.c b/lib/librte_pmd_e1000/e1000/e1000_82571.c index bd95bc911f..8ae1cb12e2 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_82571.c +++ b/lib/librte_pmd_e1000/e1000/e1000_82571.c @@ -1,6 +1,6 @@ /******************************************************************************* -Copyright (c) 2001-2012, Intel Corporation +Copyright (c) 2001-2014, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -31,8 +31,7 @@ POSSIBILITY OF SUCH DAMAGE. ***************************************************************************/ -/* - * 82571EB Gigabit Ethernet Controller +/* 82571EB Gigabit Ethernet Controller * 82571EB Gigabit Ethernet Controller (Copper) * 82571EB Gigabit Ethernet Controller (Fiber) * 82571EB Dual Port Gigabit Mezzanine Adapter @@ -50,9 +49,6 @@ POSSIBILITY OF SUCH DAMAGE. #include "e1000_api.h" -STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw); -STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); -STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw); STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); STATIC void e1000_release_nvm_82571(struct e1000_hw *hw); STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, @@ -73,20 +69,19 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); -static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); -static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); -static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); -static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); -static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); -static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); -static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); -static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); +STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); +STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); +STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw); +STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); +STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); +STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); +STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active); STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active); -static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); -static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, +STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); +STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); @@ -238,8 +233,7 @@ STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) if (((eecd >> 15) & 0x3) == 0x3) { nvm->type = e1000_nvm_flash_hw; nvm->word_size = 2048; - /* - * Autonomous Flash update bit must be cleared due + /* Autonomous Flash update bit must be cleared due * to Flash update issue. */ eecd &= ~E1000_EECD_AUPDEN; @@ -251,8 +245,7 @@ STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) nvm->type = e1000_nvm_eeprom_spi; size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> E1000_EECD_SIZE_EX_SHIFT); - /* - * Added to a constant, "size" becomes the left-shift value + /* Added to a constant, "size" becomes the left-shift value * for setting word_size. */ size += NVM_WORD_SIZE_BASE_SHIFT; @@ -379,8 +372,7 @@ STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw) /* FWSM register */ mac->has_fwsm = true; - /* - * ARC supported; valid only if manageability features are + /* ARC supported; valid only if manageability features are * enabled. */ mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & @@ -402,9 +394,8 @@ STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw) break; } - /* - * Ensure that the inter-port SWSM.SMBI lock bit is clear before - * first NVM or PHY acess. This should be done for single-port + /* Ensure that the inter-port SWSM.SMBI lock bit is clear before + * first NVM or PHY access. This should be done for single-port * devices, and for one port only on dual-port devices so that * for those devices we can still use the SMBI lock to synchronize * inter-port accesses to the PHY & NVM. @@ -441,10 +432,7 @@ STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); } - /* - * Initialze device specific counter of SMBI acquisition - * timeouts. - */ + /* Initialze device specific counter of SMBI acquisition timeouts. */ hw->dev_spec._82571.smb_counter = 0; return E1000_SUCCESS; @@ -472,7 +460,7 @@ void e1000_init_function_pointers_82571(struct e1000_hw *hw) * Reads the PHY registers and stores the PHY ID and possibly the PHY * revision in the hardware structure. **/ -static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) +STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; @@ -483,8 +471,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * The 82571 firmware may still be configuring the PHY. + /* The 82571 firmware may still be configuring the PHY. * In this case, we cannot access the PHY until the * configuration is done. So we explicitly set the * PHY ID. @@ -523,7 +510,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) * * Acquire the HW semaphore to access the PHY or NVM **/ -static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) +STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) { u32 swsm; s32 sw_timeout = hw->nvm.word_size + 1; @@ -532,8 +519,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) DEBUGFUNC("e1000_get_hw_semaphore_82571"); - /* - * If we have timedout 3 times on trying to acquire + /* If we have timedout 3 times on trying to acquire * the inter-port SMBI semaphore, there is old code * operating on the other port, and it is not * releasing SMBI. Modify the number of times that @@ -585,7 +571,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) * * Release hardware semaphore used to access the PHY or NVM **/ -static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) +STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) { u32 swsm; @@ -605,7 +591,7 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) * Acquire the HW semaphore during reset. * **/ -static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) +STATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) { u32 extcnf_ctrl; s32 i = 0; @@ -613,16 +599,14 @@ static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) DEBUGFUNC("e1000_get_hw_semaphore_82573"); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; do { + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) break; - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; - msec_delay(2); i++; } while (i < MDIO_OWNERSHIP_TIMEOUT); @@ -644,7 +628,7 @@ static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) * Release hardware semaphore used during reset. * **/ -static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) +STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) { u32 extcnf_ctrl; @@ -662,7 +646,7 @@ static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) * Acquire the HW semaphore to access the PHY or NVM. * **/ -static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) +STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) { s32 ret_val; @@ -682,7 +666,7 @@ static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) * Release hardware semaphore used to access the PHY or NVM * **/ -static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) +STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) { DEBUGFUNC("e1000_put_hw_semaphore_82574"); @@ -850,8 +834,7 @@ STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * If our nvm is an EEPROM, then we're done + /* If our nvm is an EEPROM, then we're done * otherwise, commit the checksum to the flash NVM. */ if (hw->nvm.type != e1000_nvm_flash_hw) @@ -869,8 +852,7 @@ STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) /* Reset the firmware if using STM opcode. */ if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { - /* - * The enabling of and the actual reset must be done + /* The enabling of and the actual reset must be done * in two write cycles. */ E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); @@ -925,7 +907,7 @@ STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) * If e1000_update_nvm_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. **/ -static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, +STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { struct e1000_nvm_info *nvm = &hw->nvm; @@ -934,8 +916,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, DEBUGFUNC("e1000_write_nvm_eewr_82571"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || @@ -945,9 +926,9 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, } for (i = 0; i < words; i++) { - eewr = (data[i] << E1000_NVM_RW_REG_DATA) | - ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | - E1000_NVM_RW_REG_START; + eewr = ((data[i] << E1000_NVM_RW_REG_DATA) | + ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | + E1000_NVM_RW_REG_START); ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); if (ret_val) @@ -1026,6 +1007,8 @@ STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) /* When LPLU is enabled, we should disable SmartSpeed */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + if (ret_val) + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); @@ -1035,8 +1018,7 @@ STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) data &= ~IGP02E1000_PM_D0_LPLU; ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, data); - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -1086,8 +1068,7 @@ STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) DEBUGFUNC("e1000_reset_hw_82571"); - /* - * Prevent the PCI-E bus from sticking if there is no TLP connection + /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000_disable_pcie_master_generic(hw); @@ -1105,8 +1086,7 @@ STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) msec_delay(10); - /* - * Must acquire the MDIO ownership before MAC reset. + /* Must acquire the MDIO ownership before MAC reset. * Ownership defaults to firmware after a reset. */ switch (hw->mac.type) { @@ -1120,8 +1100,6 @@ STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) default: break; } - if (ret_val) - DEBUGOUT("Cannot acquire MDIO ownership\n"); ctrl = E1000_READ_REG(hw, E1000_CTRL); @@ -1130,9 +1108,16 @@ STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) /* Must release MDIO ownership and mutex after MAC reset. */ switch (hw->mac.type) { + case e1000_82573: + /* Release mutex only if the hw semaphore is acquired */ + if (!ret_val) + e1000_put_hw_semaphore_82573(hw); + break; case e1000_82574: case e1000_82583: - e1000_put_hw_semaphore_82574(hw); + /* Release mutex only if the hw semaphore is acquired */ + if (!ret_val) + e1000_put_hw_semaphore_82574(hw); break; default: break; @@ -1151,8 +1136,7 @@ STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) /* We don't want to continue accessing MAC registers. */ return ret_val; - /* - * Phy configuration from NVM just starts after EECD_AUTO_RD is set. + /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. * Need to wait for Phy configuration completion before accessing * NVM and Phy. */ @@ -1160,8 +1144,7 @@ STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * REQ and GNT bits need to be cleared when using AUTO_RD + /* REQ and GNT bits need to be cleared when using AUTO_RD * to access the EEPROM. */ eecd = E1000_READ_REG(hw, E1000_EECD); @@ -1216,16 +1199,15 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) /* Initialize identification LED */ ret_val = mac->ops.id_led_init(hw); + /* An error is not fatal and we should not stop init due to this */ if (ret_val) DEBUGOUT("Error initializing identification LED\n"); - /* This is not fatal and we should not stop init due to this */ /* Disabling VLAN filtering */ DEBUGOUT("Initializing the IEEE VLAN\n"); mac->ops.clear_vfta(hw); - /* Setup the receive address. */ - /* + /* Setup the receive address. * If, however, a locally administered address was assigned to the * 82571, we must reserve a RAR for it to work around an issue where * resetting one port will reload the MAC on the other port. @@ -1244,8 +1226,8 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) /* Set the transmit descriptor write-back policy */ reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); - reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | - E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; + reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); /* ...for both queues. */ @@ -1261,15 +1243,14 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) break; default: reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); - reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | - E1000_TXDCTL_FULL_TX_DESC_WB | - E1000_TXDCTL_COUNT_DESC; + reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB | + E1000_TXDCTL_COUNT_DESC); E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); break; } - /* - * Clear all of the statistics registers (clear on read). It is + /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. @@ -1285,7 +1266,7 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) * * Initializes required hardware-dependent bits needed for normal operation. **/ -static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) +STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) { u32 reg; @@ -1368,8 +1349,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); } - /* - * Workaround for hardware errata. + /* Workaround for hardware errata. * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 */ if ((hw->mac.type == e1000_82571) || @@ -1379,8 +1359,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); } - /* - * Disable IPv6 extension header parsing because some malformed + /* Disable IPv6 extension header parsing because some malformed * IPv6 headers can hang the Rx. */ if (hw->mac.type <= e1000_82573) { @@ -1397,8 +1376,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) reg |= (1 << 22); E1000_WRITE_REG(hw, E1000_GCR, reg); - /* - * Workaround for hardware errata. + /* Workaround for hardware errata. * apply workaround for hardware errata documented in errata * docs Fixes issue where some error prone or unreliable PCIe * completions are occurring, particularly with ASPM enabled. @@ -1436,8 +1414,7 @@ STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw) case e1000_82574: case e1000_82583: if (hw->mng_cookie.vlan_id != 0) { - /* - * The VFTA is a 4096b bit-field, each identifying + /* The VFTA is a 4096b bit-field, each identifying * a single VLAN ID. The following operations * determine which 32b entry (i.e. offset) into the * array we want to set the VLAN ID (i.e. bit) of @@ -1455,8 +1432,7 @@ STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw) break; } for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { - /* - * If the offset we want to clear is the same offset of the + /* If the offset we want to clear is the same offset of the * manageability VLAN ID, then clear all bits except that of * the manageability unit. */ @@ -1498,8 +1474,7 @@ STATIC s32 e1000_led_on_82574(struct e1000_hw *hw) ctrl = hw->mac.ledctl_mode2; if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { - /* - * If no link, then turn LED on by setting the invert bit + /* If no link, then turn LED on by setting the invert bit * for each LED that's "on" (0x0E) in ledctl_mode2. */ for (i = 0; i < 4; i++) @@ -1522,12 +1497,11 @@ bool e1000_check_phy_82574(struct e1000_hw *hw) { u16 status_1kbt = 0; u16 receive_errors = 0; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_check_phy_82574"); - /* - * Read PHY Receive Error counter first, if its is max - all F's then + /* Read PHY Receive Error counter first, if its is max - all F's then * read the Base1000T status register If both are max then PHY is hung. */ ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, @@ -1562,8 +1536,7 @@ STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw) { DEBUGFUNC("e1000_setup_link_82571"); - /* - * 82573 does not have a word in the NVM to determine + /* 82573 does not have a word in the NVM to determine * the default flow control setting, so we explicitly * set it to full. */ @@ -1634,8 +1607,7 @@ STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * If SerDes loopback mode is entered, there is no form + /* If SerDes loopback mode is entered, there is no form * of reset to take the adapter out of that mode. So we * have to explicitly take the adapter out of loopback * mode. This prevents drivers from twiddling their thumbs @@ -1684,19 +1656,17 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); status = E1000_READ_REG(hw, E1000_STATUS); - rxcw = E1000_READ_REG(hw, E1000_RXCW); + E1000_READ_REG(hw, E1000_RXCW); /* SYNCH bit and IV bit are sticky */ usec_delay(10); rxcw = E1000_READ_REG(hw, E1000_RXCW); if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { - /* Receiver is synchronized with no invalid bits. */ switch (mac->serdes_link_state) { case e1000_serdes_link_autoneg_complete: if (!(status & E1000_STATUS_LU)) { - /* - * We have lost link, retry autoneg before + /* We have lost link, retry autoneg before * reporting link failure */ mac->serdes_link_state = @@ -1709,8 +1679,7 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) break; case e1000_serdes_link_forced_up: - /* - * If we are receiving /C/ ordered sets, re-enable + /* If we are receiving /C/ ordered sets, re-enable * auto-negotiation in the TXCW register and disable * forced link in the Device Control register in an * attempt to auto-negotiate with our link partner. @@ -1731,8 +1700,7 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) case e1000_serdes_link_autoneg_progress: if (rxcw & E1000_RXCW_C) { - /* - * We received /C/ ordered sets, meaning the + /* We received /C/ ordered sets, meaning the * link partner has autonegotiated, and we can * trust the Link Up (LU) status bit. */ @@ -1748,8 +1716,7 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) DEBUGOUT("AN_PROG -> DOWN\n"); } } else { - /* - * The link partner did not autoneg. + /* The link partner did not autoneg. * Force link up and full duplex, and change * state to forced. */ @@ -1774,8 +1741,7 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) case e1000_serdes_link_down: default: - /* - * The link was down but the receiver has now gained + /* The link was down but the receiver has now gained * valid sync, so lets see if we can bring the link * up. */ @@ -1794,8 +1760,7 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) mac->serdes_link_state = e1000_serdes_link_down; DEBUGOUT("ANYSTATE -> DOWN\n"); } else { - /* - * Check several times, if SYNCH bit and CONFIG + /* Check several times, if SYNCH bit and CONFIG * bit both are consistently 1 then simply ignore * the IV bit and restart Autoneg */ @@ -1901,8 +1866,7 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) /* If workaround is activated... */ if (state) - /* - * Hold a copy of the LAA in RAR[14] This is done so that + /* Hold a copy of the LAA in RAR[14] This is done so that * between the time RAR[0] gets clobbered and the time it * gets fixed, the actual LAA is in one of the RARs and no * incoming packets directed to this port are dropped. @@ -1923,7 +1887,7 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, * we need to return bad checksum. **/ -static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) +STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) { struct e1000_nvm_info *nvm = &hw->nvm; s32 ret_val; @@ -1934,8 +1898,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) if (nvm->type != e1000_nvm_flash_hw) return E1000_SUCCESS; - /* - * Check bit 4 of word 10h. If it is 0, firmware is done updating + /* Check bit 4 of word 10h. If it is 0, firmware is done updating * 10h-12h. Checksum may need to be fixed. */ ret_val = nvm->ops.read(hw, 0x10, 1, &data); @@ -1943,8 +1906,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) return ret_val; if (!(data & 0x10)) { - /* - * Read 0x23 and check bit 15. This bit is a 1 + /* Read 0x23 and check bit 15. This bit is a 1 * when the checksum has already been fixed. If * the checksum is still wrong and this bit is a * 1, we need to return bad checksum. Otherwise, @@ -1961,6 +1923,8 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) if (ret_val) return ret_val; ret_val = nvm->ops.update(hw); + if (ret_val) + return ret_val; } } @@ -1977,10 +1941,9 @@ STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) DEBUGFUNC("e1000_read_mac_addr_82571"); if (hw->mac.type == e1000_82571) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; - /* - * If there's an alternate MAC address place it in RAR0 + /* If there's an alternate MAC address place it in RAR0 * so that it will override the Si installed default perm * address. */