X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_pmd_e1000%2Figb_rxtx.c;h=b53e7f74f7deded60aefa1782479e939ba092d01;hb=3031749c2df04a63cdcef186dcce3781e61436e8;hp=9e3bec5d86d332c89c59eb1c2a8a37325b1864d2;hpb=e9d48c0072d36eb6423b45fba4ec49d0def6c36f;p=dpdk.git diff --git a/lib/librte_pmd_e1000/igb_rxtx.c b/lib/librte_pmd_e1000/igb_rxtx.c index 9e3bec5d86..b53e7f74f7 100644 --- a/lib/librte_pmd_e1000/igb_rxtx.c +++ b/lib/librte_pmd_e1000/igb_rxtx.c @@ -1,13 +1,13 @@ /*- * BSD LICENSE - * + * * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright @@ -17,7 +17,7 @@ * * Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -33,7 +33,6 @@ #include -#include #include #include #include @@ -1086,8 +1085,13 @@ ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name, if (mz) return mz; +#ifdef RTE_LIBRTE_XEN_DOM0 + return rte_memzone_reserve_bounded(z_name, ring_size, + socket_id, 0, IGB_ALIGN, RTE_PGSIZE_2M); +#else return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0, IGB_ALIGN); +#endif } static void @@ -1234,15 +1238,20 @@ eth_igb_tx_queue_setup(struct rte_eth_dev *dev, txq->pthresh = tx_conf->tx_thresh.pthresh; txq->hthresh = tx_conf->tx_thresh.hthresh; txq->wthresh = tx_conf->tx_thresh.wthresh; + if (txq->wthresh > 0 && hw->mac.type == e1000_82576) + txq->wthresh = 1; txq->queue_id = queue_idx; txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ? queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx); txq->port_id = dev->data->port_id; txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx)); +#ifndef RTE_LIBRTE_XEN_DOM0 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr; - txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr; - +#else + txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr); +#endif + txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr; /* Allocate software ring */ txq->sw_ring = rte_zmalloc("txq->sw_ring", sizeof(struct igb_tx_entry) * nb_desc, @@ -1350,6 +1359,8 @@ eth_igb_rx_queue_setup(struct rte_eth_dev *dev, rxq->pthresh = rx_conf->rx_thresh.pthresh; rxq->hthresh = rx_conf->rx_thresh.hthresh; rxq->wthresh = rx_conf->rx_thresh.wthresh; + if (rxq->wthresh > 0 && hw->mac.type == e1000_82576) + rxq->wthresh = 1; rxq->drop_en = rx_conf->rx_drop_en; rxq->rx_free_thresh = rx_conf->rx_free_thresh; rxq->queue_id = queue_idx; @@ -1372,7 +1383,11 @@ eth_igb_rx_queue_setup(struct rte_eth_dev *dev, } rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx)); rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx)); +#ifndef RTE_LIBRTE_XEN_DOM0 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr; +#else + rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr); +#endif rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr; /* Allocate software ring. */ @@ -1392,7 +1407,7 @@ eth_igb_rx_queue_setup(struct rte_eth_dev *dev, return 0; } -uint32_t +uint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { #define IGB_RXQ_SCAN_INTERVAL 4 @@ -1504,53 +1519,28 @@ igb_rss_disable(struct rte_eth_dev *dev) } static void -igb_rss_configure(struct rte_eth_dev *dev) +igb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf) { - struct e1000_hw *hw; - uint8_t *hash_key; + uint8_t *hash_key; uint32_t rss_key; uint32_t mrqc; - uint32_t shift; uint16_t rss_hf; uint16_t i; - hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - - rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf; - if (rss_hf == 0) /* Disable RSS. */ { - igb_rss_disable(dev); - return; - } - hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; - if (hash_key == NULL) - hash_key = rss_intel_key; /* Default hash key. */ - - /* Fill in RSS hash key. */ - for (i = 0; i < 10; i++) { - rss_key = hash_key[(i * 4)]; - rss_key |= hash_key[(i * 4) + 1] << 8; - rss_key |= hash_key[(i * 4) + 2] << 16; - rss_key |= hash_key[(i * 4) + 3] << 24; - E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key); - } - - /* Fill in redirection table. */ - shift = (hw->mac.type == e1000_82575) ? 6 : 0; - for (i = 0; i < 128; i++) { - union e1000_reta { - uint32_t dword; - uint8_t bytes[4]; - } reta; - uint8_t q_idx; - - q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ? - i % dev->data->nb_rx_queues : 0); - reta.bytes[i & 3] = (uint8_t) (q_idx << shift); - if ((i & 3) == 3) - E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword); + hash_key = rss_conf->rss_key; + if (hash_key != NULL) { + /* Fill in RSS hash key */ + for (i = 0; i < 10; i++) { + rss_key = hash_key[(i * 4)]; + rss_key |= hash_key[(i * 4) + 1] << 8; + rss_key |= hash_key[(i * 4) + 2] << 16; + rss_key |= hash_key[(i * 4) + 3] << 24; + E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key); + } } - /* Set configured hashing functions in MRQC register. */ + /* Set configured hashing protocols in MRQC register */ + rss_hf = rss_conf->rss_hf; mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */ if (rss_hf & ETH_RSS_IPV4) mrqc |= E1000_MRQC_RSS_FIELD_IPV4; @@ -1573,6 +1563,128 @@ igb_rss_configure(struct rte_eth_dev *dev) E1000_WRITE_REG(hw, E1000_MRQC, mrqc); } +int +eth_igb_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct e1000_hw *hw; + uint32_t mrqc; + uint16_t rss_hf; + + hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* + * Before changing anything, first check that the update RSS operation + * does not attempt to disable RSS, if RSS was enabled at + * initialization time, or does not attempt to enable RSS, if RSS was + * disabled at initialization time. + */ + rss_hf = rss_conf->rss_hf; + mrqc = E1000_READ_REG(hw, E1000_MRQC); + if (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */ + if (rss_hf != 0) /* Enable RSS */ + return -(EINVAL); + return 0; /* Nothing to do */ + } + /* RSS enabled */ + if (rss_hf == 0) /* Disable RSS */ + return -(EINVAL); + igb_hw_rss_hash_set(hw, rss_conf); + return 0; +} + +int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct e1000_hw *hw; + uint8_t *hash_key; + uint32_t rss_key; + uint32_t mrqc; + uint16_t rss_hf; + uint16_t i; + + hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + hash_key = rss_conf->rss_key; + if (hash_key != NULL) { + /* Return RSS hash key */ + for (i = 0; i < 10; i++) { + rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i); + hash_key[(i * 4)] = rss_key & 0x000000FF; + hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF; + hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF; + hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF; + } + } + + /* Get RSS functions configured in MRQC register */ + mrqc = E1000_READ_REG(hw, E1000_MRQC); + if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */ + rss_conf->rss_hf = 0; + return 0; + } + rss_hf = 0; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV4) + rss_hf |= ETH_RSS_IPV4; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP) + rss_hf |= ETH_RSS_IPV4_TCP; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV6) + rss_hf |= ETH_RSS_IPV6; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX) + rss_hf |= ETH_RSS_IPV6_EX; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP) + rss_hf |= ETH_RSS_IPV6_TCP; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX) + rss_hf |= ETH_RSS_IPV6_TCP_EX; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP) + rss_hf |= ETH_RSS_IPV4_UDP; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP) + rss_hf |= ETH_RSS_IPV6_UDP; + if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX) + rss_hf |= ETH_RSS_IPV6_UDP_EX; + rss_conf->rss_hf = rss_hf; + return 0; +} + +static void +igb_rss_configure(struct rte_eth_dev *dev) +{ + struct rte_eth_rss_conf rss_conf; + struct e1000_hw *hw; + uint32_t shift; + uint16_t i; + + hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* Fill in redirection table. */ + shift = (hw->mac.type == e1000_82575) ? 6 : 0; + for (i = 0; i < 128; i++) { + union e1000_reta { + uint32_t dword; + uint8_t bytes[4]; + } reta; + uint8_t q_idx; + + q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ? + i % dev->data->nb_rx_queues : 0); + reta.bytes[i & 3] = (uint8_t) (q_idx << shift); + if ((i & 3) == 3) + E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword); + } + + /* + * Configure the RSS key and the RSS protocols used to compute + * the RSS hash of input packets. + */ + rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf; + if (rss_conf.rss_hf == 0) { + igb_rss_disable(dev); + return; + } + if (rss_conf.rss_key == NULL) + rss_conf.rss_key = rss_intel_key; /* Default hash key */ + igb_hw_rss_hash_set(hw, &rss_conf); +} + /* * Check if the mac type support VMDq or not. * Return 1 if it supports, otherwise, return 0. @@ -1581,27 +1693,27 @@ static int igb_is_vmdq_supported(const struct rte_eth_dev *dev) { const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - - switch (hw->mac.type) { - case e1000_82576: - case e1000_82580: - case e1000_i350: + + switch (hw->mac.type) { + case e1000_82576: + case e1000_82580: + case e1000_i350: return 1; - case e1000_82540: - case e1000_82541: - case e1000_82542: - case e1000_82543: - case e1000_82544: - case e1000_82545: - case e1000_82546: - case e1000_82547: - case e1000_82571: - case e1000_82572: - case e1000_82573: - case e1000_82574: - case e1000_82583: - case e1000_i210: - case e1000_i211: + case e1000_82540: + case e1000_82541: + case e1000_82542: + case e1000_82543: + case e1000_82544: + case e1000_82545: + case e1000_82546: + case e1000_82547: + case e1000_82571: + case e1000_82572: + case e1000_82573: + case e1000_82574: + case e1000_82583: + case e1000_i210: + case e1000_i211: default: PMD_INIT_LOG(ERR, "Cannot support VMDq feature\n"); return 0; @@ -1615,8 +1727,8 @@ igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev) struct e1000_hw *hw; uint32_t mrqc, vt_ctl, vmolr, rctl; int i; - - PMD_INIT_LOG(DEBUG, ">>"); + + PMD_INIT_LOG(DEBUG, ">>"); hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf; @@ -1625,7 +1737,7 @@ igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev) return -1; igb_rss_disable(dev); - + /* RCTL: eanble VLAN filter */ rctl = E1000_READ_REG(hw, E1000_RCTL); rctl |= E1000_RCTL_VFE; @@ -1633,20 +1745,20 @@ igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev) /* MRQC: enable vmdq */ mrqc = E1000_READ_REG(hw, E1000_MRQC); - mrqc |= E1000_MRQC_ENABLE_VMDQ; + mrqc |= E1000_MRQC_ENABLE_VMDQ; E1000_WRITE_REG(hw, E1000_MRQC, mrqc); - + /* VTCTL: pool selection according to VLAN tag */ vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); - if (cfg->enable_default_pool) + if (cfg->enable_default_pool) vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT); vt_ctl |= E1000_VT_CTL_IGNORE_MAC; E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); - - /* + + /* * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1 - * Both 82576 and 82580 support it - */ + * Both 82576 and 82580 support it + */ if (hw->mac.type != e1000_i350) { for (i = 0; i < E1000_VMOLR_SIZE; i++) { vmolr = E1000_READ_REG(hw, E1000_VMOLR(i)); @@ -1656,13 +1768,13 @@ igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev) } /* VFTA - enable all vlan filters */ - for (i = 0; i < IGB_VFTA_SIZE; i++) + for (i = 0; i < IGB_VFTA_SIZE; i++) E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX); - + /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */ if (hw->mac.type != e1000_82580) E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK); - + /* * RAH/RAL - allow pools to read specific mac addresses * In this case, all pools should be able to read from mac addr 0 @@ -1680,7 +1792,7 @@ igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev) } E1000_WRITE_FLUSH(hw); - + return 0; } @@ -1727,42 +1839,39 @@ igb_dev_mq_rx_configure(struct rte_eth_dev *dev) struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t mrqc; - + if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) { /* - * SRIOV active scheme - * FIXME if support RSS together with VMDq & SRIOV - */ + * SRIOV active scheme + * FIXME if support RSS together with VMDq & SRIOV + */ mrqc = E1000_MRQC_ENABLE_VMDQ; /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */ mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT; E1000_WRITE_REG(hw, E1000_MRQC, mrqc); - } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) { + } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) { /* - * SRIOV inactive scheme - */ - if (dev->data->nb_rx_queues > 1) - switch (dev->data->dev_conf.rxmode.mq_mode) { - case ETH_MQ_RX_NONE: - /* if mq_mode not assign, we use rss mode.*/ + * SRIOV inactive scheme + */ + switch (dev->data->dev_conf.rxmode.mq_mode) { case ETH_MQ_RX_RSS: igb_rss_configure(dev); break; case ETH_MQ_RX_VMDQ_ONLY: /*Configure general VMDQ only RX parameters*/ - igb_vmdq_rx_hw_configure(dev); + igb_vmdq_rx_hw_configure(dev); break; - default: + case ETH_MQ_RX_NONE: + /* if mq_mode is none, disable rss mode.*/ + default: igb_rss_disable(dev); break; - } - else - igb_rss_disable(dev); + } } - + return 0; } - + int eth_igb_rx_init(struct rte_eth_dev *dev) { @@ -1838,8 +1947,7 @@ eth_igb_rx_init(struct rte_eth_dev *dev) /* * Configure RX buffer size. */ - mbp_priv = (struct rte_pktmbuf_pool_private *) - ((char *)rxq->mb_pool + sizeof(struct rte_mempool)); + mbp_priv = rte_mempool_get_priv(rxq->mb_pool); buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM); if (buf_size >= 1024) { @@ -2066,6 +2174,11 @@ eth_igbvf_rx_init(struct rte_eth_dev *dev) hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + /* setup MTU */ + e1000_rlpml_set_vf(hw, + (uint16_t)(dev->data->dev_conf.rxmode.max_rx_pkt_len + + VLAN_TAG_SIZE)); + /* Configure and enable each RX queue. */ rctl_bsize = 0; dev->rx_pkt_burst = eth_igb_recv_pkts; @@ -2093,8 +2206,7 @@ eth_igbvf_rx_init(struct rte_eth_dev *dev) /* * Configure RX buffer size. */ - mbp_priv = (struct rte_pktmbuf_pool_private *) - ((char *)rxq->mb_pool + sizeof(struct rte_mempool)); + mbp_priv = rte_mempool_get_priv(rxq->mb_pool); buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM); if (buf_size >= 1024) { @@ -2139,10 +2251,10 @@ eth_igbvf_rx_init(struct rte_eth_dev *dev) rxdctl &= 0xFFF00000; rxdctl |= (rxq->pthresh & 0x1F); rxdctl |= ((rxq->hthresh & 0x1F) << 8); - if (hw->mac.type == e1000_82576) { - /* + if (hw->mac.type == e1000_vfadapt) { + /* * Workaround of 82576 VF Erratum - * force set WTHRESH to 1 + * force set WTHRESH to 1 * to avoid Write-Back not triggered sometimes */ rxdctl |= 0x10000; @@ -2203,12 +2315,12 @@ eth_igbvf_tx_init(struct rte_eth_dev *dev) txdctl |= txq->pthresh & 0x1F; txdctl |= ((txq->hthresh & 0x1F) << 8); if (hw->mac.type == e1000_82576) { - /* + /* * Workaround of 82576 VF Erratum - * force set WTHRESH to 1 + * force set WTHRESH to 1 * to avoid Write-Back not triggered sometimes */ - txdctl |= 0x10000; + txdctl |= 0x10000; PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !\n"); } else