X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_pmd_i40e%2Fi40e_ethdev_vf.c;h=7d8d8ef06f0f4ace476da85e5817cdb6f4cc336d;hb=4e4510dfff548eab47da112b8fb7c48a33f0f959;hp=966f02f2bb9c1f4654b33c6b7f8dcae3c20cbf46;hpb=5e904375a4d6aa48282a7c95c55e32b538ab26ab;p=dpdk.git

diff --git a/lib/librte_pmd_i40e/i40e_ethdev_vf.c b/lib/librte_pmd_i40e/i40e_ethdev_vf.c
index 966f02f2bb..7d8d8ef06f 100644
--- a/lib/librte_pmd_i40e/i40e_ethdev_vf.c
+++ b/lib/librte_pmd_i40e/i40e_ethdev_vf.c
@@ -126,15 +126,25 @@ static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 static int i40evf_get_link_status(struct rte_eth_dev *dev,
 				  struct rte_eth_link *link);
 static int i40evf_init_vlan(struct rte_eth_dev *dev);
+static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
+				     uint16_t rx_queue_id);
+static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
+				    uint16_t rx_queue_id);
+static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
+				     uint16_t tx_queue_id);
+static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
+				    uint16_t tx_queue_id);
+static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
+			struct rte_eth_rss_reta_entry64 *reta_conf,
+			uint16_t reta_size);
+static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
+			struct rte_eth_rss_reta_entry64 *reta_conf,
+			uint16_t reta_size);
 static int i40evf_config_rss(struct i40e_vf *vf);
 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 				      struct rte_eth_rss_conf *rss_conf);
 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 					struct rte_eth_rss_conf *rss_conf);
-static int i40evf_dev_rx_queue_start(struct rte_eth_dev *, uint16_t);
-static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *, uint16_t);
-static int i40evf_dev_tx_queue_start(struct rte_eth_dev *, uint16_t);
-static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *, uint16_t);
 
 /* Default hash key buffer for RSS */
 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
@@ -162,6 +172,8 @@ static struct eth_dev_ops i40evf_eth_dev_ops = {
 	.rx_queue_release     = i40e_dev_rx_queue_release,
 	.tx_queue_setup       = i40e_dev_tx_queue_setup,
 	.tx_queue_release     = i40e_dev_tx_queue_release,
+	.reta_update          = i40evf_dev_rss_reta_update,
+	.reta_query           = i40evf_dev_rss_reta_query,
 	.rss_hash_update      = i40evf_dev_rss_hash_update,
 	.rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 };
@@ -533,82 +545,151 @@ i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 	return err;
 }
 
+static void
+i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
+				  uint16_t vsi_id,
+				  uint16_t queue_id,
+				  uint16_t nb_txq,
+				  struct i40e_tx_queue *txq)
+{
+	txq_info->vsi_id = vsi_id;
+	txq_info->queue_id = queue_id;
+	if (queue_id < nb_txq) {
+		txq_info->ring_len = txq->nb_tx_desc;
+		txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
+	}
+}
+
+static void
+i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
+				  uint16_t vsi_id,
+				  uint16_t queue_id,
+				  uint16_t nb_rxq,
+				  uint32_t max_pkt_size,
+				  struct i40e_rx_queue *rxq)
+{
+	rxq_info->vsi_id = vsi_id;
+	rxq_info->queue_id = queue_id;
+	rxq_info->max_pkt_size = max_pkt_size;
+	if (queue_id < nb_rxq) {
+		struct rte_pktmbuf_pool_private *mbp_priv;
+
+		rxq_info->ring_len = rxq->nb_rx_desc;
+		rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
+		mbp_priv = rte_mempool_get_priv(rxq->mp);
+		rxq_info->databuffer_size =
+			mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
+	}
+}
+
+/* It configures VSI queues to co-work with Linux PF host */
 static int
-i40evf_configure_queues(struct rte_eth_dev *dev)
+i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 {
 	struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
-	struct i40e_virtchnl_vsi_queue_config_info *queue_info;
-	struct i40e_virtchnl_queue_pair_info *queue_cfg;
 	struct i40e_rx_queue **rxq =
 		(struct i40e_rx_queue **)dev->data->rx_queues;
 	struct i40e_tx_queue **txq =
 		(struct i40e_tx_queue **)dev->data->tx_queues;
-	int i, len, nb_qpairs, num_rxq, num_txq;
-	int err;
+	struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
+	struct i40e_virtchnl_queue_pair_info *vc_qpi;
 	struct vf_cmd_info args;
-	struct rte_pktmbuf_pool_private *mbp_priv;
+	uint16_t i, nb_qp = vf->num_queue_pairs;
+	const uint32_t size =
+		I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
+	uint8_t buff[size];
+	int ret;
 
-	nb_qpairs = vf->num_queue_pairs;
-	len = sizeof(*queue_info) + sizeof(*queue_cfg) * nb_qpairs;
-	queue_info = rte_zmalloc("queue_info", len, 0);
-	if (queue_info == NULL) {
-		PMD_INIT_LOG(ERR, "failed alloc memory for queue_info");
-		return -1;
+	memset(buff, 0, sizeof(buff));
+	vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
+	vc_vqci->vsi_id = vf->vsi_res->vsi_id;
+	vc_vqci->num_queue_pairs = nb_qp;
+
+	for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
+		i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
+			vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
+		i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
+			vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
+					vf->max_pkt_len, rxq[i]);
 	}
-	queue_info->vsi_id = vf->vsi_res->vsi_id;
-	queue_info->num_queue_pairs = nb_qpairs;
-	queue_cfg = queue_info->qpair;
+	memset(&args, 0, sizeof(args));
+	args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
+	args.in_args = (uint8_t *)vc_vqci;
+	args.in_args_size = size;
+	args.out_buffer = cmd_result_buffer;
+	args.out_size = I40E_AQ_BUF_SZ;
+	ret = i40evf_execute_vf_cmd(dev, &args);
+	if (ret)
+		PMD_DRV_LOG(ERR, "Failed to execute command of "
+			"I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
 
-	num_rxq = dev->data->nb_rx_queues;
-	num_txq = dev->data->nb_tx_queues;
-	/*
-	 * PF host driver required to configure queues in pairs, which means
-	 * rxq_num should equals to txq_num. The actual usage won't always
-	 * work that way. The solution is fills 0 with HW ring option in case
-	 * they are not equal.
-	 */
-	for (i = 0; i < nb_qpairs; i++) {
-		/*Fill TX info */
-		queue_cfg->txq.vsi_id = queue_info->vsi_id;
-		queue_cfg->txq.queue_id = i;
-		if (i < num_txq) {
-			queue_cfg->txq.ring_len = txq[i]->nb_tx_desc;
-			queue_cfg->txq.dma_ring_addr = txq[i]->tx_ring_phys_addr;
-		} else {
-			queue_cfg->txq.ring_len = 0;
-			queue_cfg->txq.dma_ring_addr = 0;
-		}
+	return ret;
+}
 
-		/* Fill RX info */
-		queue_cfg->rxq.vsi_id = queue_info->vsi_id;
-		queue_cfg->rxq.queue_id = i;
-		queue_cfg->rxq.max_pkt_size = vf->max_pkt_len;
-		if (i < num_rxq) {
-			mbp_priv = rte_mempool_get_priv(rxq[i]->mp);
-			queue_cfg->rxq.databuffer_size = mbp_priv->mbuf_data_room_size -
-						   RTE_PKTMBUF_HEADROOM;;
-			queue_cfg->rxq.ring_len = rxq[i]->nb_rx_desc;
-			queue_cfg->rxq.dma_ring_addr = rxq[i]->rx_ring_phys_addr;;
-		} else {
-			queue_cfg->rxq.ring_len = 0;
-			queue_cfg->rxq.dma_ring_addr = 0;
-			queue_cfg->rxq.databuffer_size = 0;
-		}
-		queue_cfg++;
-	}
+/* It configures VSI queues to co-work with DPDK PF host */
+static int
+i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
+{
+	struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
+	struct i40e_rx_queue **rxq =
+		(struct i40e_rx_queue **)dev->data->rx_queues;
+	struct i40e_tx_queue **txq =
+		(struct i40e_tx_queue **)dev->data->tx_queues;
+	struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
+	struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
+	struct vf_cmd_info args;
+	uint16_t i, nb_qp = vf->num_queue_pairs;
+	const uint32_t size =
+		I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
+	uint8_t buff[size];
+	int ret;
 
-	args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
-	args.in_args = (u8 *)queue_info;
-	args.in_args_size = len;
+	memset(buff, 0, sizeof(buff));
+	vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
+	vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
+	vc_vqcei->num_queue_pairs = nb_qp;
+	vc_qpei = vc_vqcei->qpair;
+	for (i = 0; i < nb_qp; i++, vc_qpei++) {
+		i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
+			vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
+		i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
+			vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
+					vf->max_pkt_len, rxq[i]);
+		if (i < dev->data->nb_rx_queues)
+			/*
+			 * It adds extra info for configuring VSI queues, which
+			 * is needed to enable the configurable crc stripping
+			 * in VF.
+			 */
+			vc_qpei->rxq_ext.crcstrip =
+				dev->data->dev_conf.rxmode.hw_strip_crc;
+	}
+	memset(&args, 0, sizeof(args));
+	args.ops =
+		(enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
+	args.in_args = (uint8_t *)vc_vqcei;
+	args.in_args_size = size;
 	args.out_buffer = cmd_result_buffer;
 	args.out_size = I40E_AQ_BUF_SZ;
-	err = i40evf_execute_vf_cmd(dev, &args);
-	if (err)
-		PMD_DRV_LOG(ERR, "fail to execute command "
-			    "OP_CONFIG_VSI_QUEUES");
-	rte_free(queue_info);
+	ret = i40evf_execute_vf_cmd(dev, &args);
+	if (ret)
+		PMD_DRV_LOG(ERR, "Failed to execute command of "
+			"I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
 
-	return err;
+	return ret;
+}
+
+static int
+i40evf_configure_queues(struct rte_eth_dev *dev)
+{
+	struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
+
+	if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
+		/* To support DPDK PF host */
+		return i40evf_configure_vsi_queues_ext(dev);
+	else
+		/* To support Linux PF host */
+		return i40evf_configure_vsi_queues(dev);
 }
 
 static int
@@ -1564,12 +1645,34 @@ i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
 	dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
 	dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
+	dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
+
+	dev_info->default_rxconf = (struct rte_eth_rxconf) {
+		.rx_thresh = {
+			.pthresh = I40E_DEFAULT_RX_PTHRESH,
+			.hthresh = I40E_DEFAULT_RX_HTHRESH,
+			.wthresh = I40E_DEFAULT_RX_WTHRESH,
+		},
+		.rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
+		.rx_drop_en = 0,
+	};
+
+	dev_info->default_txconf = (struct rte_eth_txconf) {
+		.tx_thresh = {
+			.pthresh = I40E_DEFAULT_TX_PTHRESH,
+			.hthresh = I40E_DEFAULT_TX_HTHRESH,
+			.wthresh = I40E_DEFAULT_TX_WTHRESH,
+		},
+		.tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
+		.tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
+		.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
+				ETH_TXQ_FLAGS_NOOFFLOADS,
+	};
 }
 
 static void
 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 {
-	memset(stats, 0, sizeof(*stats));
 	if (i40evf_get_statics(dev, stats))
 		PMD_DRV_LOG(ERR, "Get statics failed");
 }
@@ -1584,6 +1687,87 @@ i40evf_dev_close(struct rte_eth_dev *dev)
 	i40e_shutdown_adminq(hw);
 }
 
+static int
+i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
+			   struct rte_eth_rss_reta_entry64 *reta_conf,
+			   uint16_t reta_size)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t lut, l;
+	uint16_t i, j;
+	uint16_t idx, shift;
+	uint8_t mask;
+
+	if (reta_size != ETH_RSS_RETA_SIZE_64) {
+		PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
+			"(%d) doesn't match the number of hardware can "
+			"support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
+		idx = i / RTE_RETA_GROUP_SIZE;
+		shift = i % RTE_RETA_GROUP_SIZE;
+		mask = (uint8_t)((reta_conf[idx].mask >> shift) &
+						I40E_4_BIT_MASK);
+		if (!mask)
+			continue;
+		if (mask == I40E_4_BIT_MASK)
+			l = 0;
+		else
+			l = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));
+
+		for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
+			if (mask & (0x1 << j))
+				lut |= reta_conf[idx].reta[shift + j] <<
+							(CHAR_BIT * j);
+			else
+				lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
+		}
+		I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
+	}
+
+	return 0;
+}
+
+static int
+i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
+			  struct rte_eth_rss_reta_entry64 *reta_conf,
+			  uint16_t reta_size)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t lut;
+	uint16_t i, j;
+	uint16_t idx, shift;
+	uint8_t mask;
+
+	if (reta_size != ETH_RSS_RETA_SIZE_64) {
+		PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
+			"(%d) doesn't match the number of hardware can "
+			"support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
+		idx = i / RTE_RETA_GROUP_SIZE;
+		shift = i % RTE_RETA_GROUP_SIZE;
+		mask = (uint8_t)((reta_conf[idx].mask >> shift) &
+						I40E_4_BIT_MASK);
+		if (!mask)
+			continue;
+
+		lut = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));
+		for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
+			if (mask & (0x1 << j))
+				reta_conf[idx].reta[shift + j] =
+					((lut >> (CHAR_BIT * j)) &
+						I40E_8_BIT_MASK);
+		}
+	}
+
+	return 0;
+}
+
 static int
 i40evf_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
 {