X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_pmd_ixgbe%2Fixgbe_rxtx.h;h=329007cbd6c08fdeb70288df579faf882fb3da8f;hb=54292e9520e0;hp=64c0695b2fef611692aa8cf76ae87c8f661021c5;hpb=b23dad37f0c745b6cab1c90f8e136584c4c8d15b;p=dpdk.git diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.h b/lib/librte_pmd_ixgbe/ixgbe_rxtx.h index 64c0695b2f..329007cbd6 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.h +++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.h @@ -47,8 +47,7 @@ #endif #define RTE_MBUF_DATA_DMA_ADDR(mb) \ - (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \ - (char *)(mb)->buf_addr)) + (uint64_t) ((mb)->buf_physaddr + (mb)->data_off) #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \ (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM) @@ -96,14 +95,6 @@ struct igb_tx_entry_v { struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ }; -/** - * continuous entry sequence, gather by the same mempool - */ -struct igb_tx_entry_seq { - const struct rte_mempool* pool; - uint32_t same_pool; -}; - /** * Structure associated with each RX queue. */ @@ -116,6 +107,7 @@ struct igb_rx_queue { struct igb_rx_entry *sw_ring; /**< address of RX software ring. */ struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */ struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */ + uint64_t mbuf_initializer; /**< value to init mbufs */ uint16_t nb_rx_desc; /**< number of RX descriptors. */ uint16_t rx_tail; /**< current value of RDT register. */ uint16_t nb_rx_hold; /**< number of held free RX desc. */ @@ -127,7 +119,6 @@ struct igb_rx_queue { #ifdef RTE_IXGBE_INC_VECTOR uint16_t rxrearm_nb; /**< the idx we start the re-arming from */ uint16_t rxrearm_start; /**< number of remaining to be re-armed */ - __m128i misc_info; /**< cache XMM combine port_id/crc/nb_segs */ #endif uint16_t rx_free_thresh; /**< max free RX desc to hold. */ uint16_t queue_id; /**< RX queue index. */ @@ -135,7 +126,7 @@ struct igb_rx_queue { uint8_t port_id; /**< Device port identifier. */ uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */ uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */ - uint8_t start_rx_per_q; + uint8_t rx_deferred_start; /**< not in global dev start. */ #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC /** need to alloc dummy mbuf, for wraparound when scanning hw ring */ struct rte_mbuf fake_mbuf; @@ -153,14 +144,39 @@ enum ixgbe_advctx_num { IXGBE_CTX_NUM = 2, /**< CTX NUMBER */ }; +/** Offload features */ +union ixgbe_tx_offload { + uint64_t data; + struct { + uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ + uint64_t l3_len:9; /**< L3 (IP) Header Length. */ + uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ + uint64_t tso_segsz:16; /**< TCP TSO segment size */ + uint64_t vlan_tci:16; + /**< VLAN Tag Control Identifier (CPU order). */ + }; +}; + +/* + * Compare mask for vlan_macip_len.data, + * should be in sync with ixgbe_vlan_macip.f layout. + * */ +#define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */ +#define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */ +#define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */ +/** MAC+IP length. */ +#define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK) + /** * Structure to check if new context need be built */ struct ixgbe_advctx_info { - uint16_t flags; /**< ol_flags for context build. */ - uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */ - union rte_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */ + uint64_t flags; /**< ol_flags for context build. */ + /**< tx offload: vlan, tso, l2-l3-l4 lengths. */ + union ixgbe_tx_offload tx_offload; + /** compare mask for tx offload. */ + union ixgbe_tx_offload tx_offload_mask; }; /** @@ -171,10 +187,6 @@ struct igb_tx_queue { volatile union ixgbe_adv_tx_desc *tx_ring; uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */ -#ifdef RTE_IXGBE_INC_VECTOR - /** continuous tx entry sequence within the same mempool */ - struct igb_tx_entry_seq *sw_ring_seq; -#endif volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ uint16_t nb_tx_desc; /**< number of TX descriptors. */ uint16_t tx_tail; /**< current value of TDT reg. */ @@ -200,7 +212,7 @@ struct igb_tx_queue { /** Hardware context0 history. */ struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM]; struct ixgbe_txq_ops *ops; /**< txq ops */ - uint8_t start_tx_per_q; + uint8_t tx_deferred_start; /**< not in global dev start. */ }; struct ixgbe_txq_ops { @@ -236,11 +248,22 @@ struct ixgbe_txq_ops { IXGBE_ADVTXD_DCMD_DEXT |\ IXGBE_ADVTXD_DCMD_EOP) + +/* Takes an ethdev and a queue and sets up the tx function to be used based on + * the queue parameters. Used in tx_queue_setup by primary process and then + * in dev_init by secondary process when attaching to an existing ethdev. + */ +void set_tx_function(struct rte_eth_dev *dev, struct igb_tx_queue *txq); + #ifdef RTE_IXGBE_INC_VECTOR -uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); -uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); -int ixgbe_txq_vec_setup(struct igb_tx_queue *txq, unsigned int socket_id); -int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq, unsigned int socket_id); +uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); +uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue, + struct rte_mbuf **rx_pkts, uint16_t nb_pkts); +uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); +int ixgbe_txq_vec_setup(struct igb_tx_queue *txq); +int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq); int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev); #endif