From: Qi Zhang Date: Mon, 6 Jan 2020 03:38:40 +0000 (+0800) Subject: net/ice/base: whitelist register for NVM access X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;ds=sidebyside;h=e0e325065bee98dade424f2e68a8b473a83ac2f5;p=dpdk.git net/ice/base: whitelist register for NVM access Allow tools to access register offset 0xB8188 (GLGEN_RSTAT) for NVMUpdate operations. This is a read-only register, so risk of other issues stemming from this change is low. Even so, update the write command to prevent and reject any commands which attempt to write to this register, just like we do for GL_HICR_EN. Signed-off-by: Jeb Cramer Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 1dbfc2dcc7..2d92524f27 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -504,6 +504,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd) case GL_FWSTS: case GL_MNG_FWSM: case GLGEN_CSR_DEBUG_C: + case GLGEN_RSTAT: case GLPCI_LBARCTRL: case GLNVM_GENS: case GLNVM_FLA: @@ -579,9 +580,14 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, if (status) return status; - /* The HICR_EN register is read-only */ - if (cmd->offset == GL_HICR_EN) + /* Reject requests to write to read-only registers */ + switch (cmd->offset) { + case GL_HICR_EN: + case GLGEN_RSTAT: return ICE_ERR_OUT_OF_RANGE; + default: + break; + } ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",