From: Intel <intel.com>
Date: Wed, 19 Dec 2012 23:00:00 +0000 (+0100)
Subject: ethdev: add DCB support
X-Git-Tag: spdx-start~11369
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=041cdbf947fa7eb732e67b1c691c2572c7513461;p=dpdk.git

ethdev: add DCB support

Signed-off-by: Intel
---

diff --git a/examples/exception_path/main.c b/examples/exception_path/main.c
index f1f52d99b0..646065ced3 100644
--- a/examples/exception_path/main.c
+++ b/examples/exception_path/main.c
@@ -148,6 +148,7 @@ static const struct rte_eth_conf port_conf = {
 		.hw_strip_crc = 0,      /* CRC stripped by hardware */
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/ipv4_frag/main.c b/examples/ipv4_frag/main.c
index 5983986342..a790d936b4 100644
--- a/examples/ipv4_frag/main.c
+++ b/examples/ipv4_frag/main.c
@@ -167,6 +167,7 @@ static const struct rte_eth_conf port_conf = {
 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/ipv4_multicast/main.c b/examples/ipv4_multicast/main.c
index 0ae8c3c8cc..356bb6439b 100644
--- a/examples/ipv4_multicast/main.c
+++ b/examples/ipv4_multicast/main.c
@@ -176,6 +176,7 @@ static const struct rte_eth_conf port_conf = {
 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/l2fwd/main.c b/examples/l2fwd/main.c
index 6731a14a97..5ed37b80f6 100644
--- a/examples/l2fwd/main.c
+++ b/examples/l2fwd/main.c
@@ -151,6 +151,7 @@ static const struct rte_eth_conf port_conf = {
 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/l3fwd-vf/main.c b/examples/l3fwd-vf/main.c
index ead3cb85f0..e3a999ae88 100644
--- a/examples/l3fwd-vf/main.c
+++ b/examples/l3fwd-vf/main.c
@@ -197,6 +197,7 @@ static struct rte_eth_conf port_conf = {
 		},
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/l3fwd/main.c b/examples/l3fwd/main.c
index 4d579c16de..6ca4ab290f 100644
--- a/examples/l3fwd/main.c
+++ b/examples/l3fwd/main.c
@@ -198,6 +198,7 @@ static struct rte_eth_conf port_conf = {
 		},
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/link_status_interrupt/main.c b/examples/link_status_interrupt/main.c
index 5f0fad6c93..b6a46223d7 100644
--- a/examples/link_status_interrupt/main.c
+++ b/examples/link_status_interrupt/main.c
@@ -151,6 +151,7 @@ static const struct rte_eth_conf port_conf = {
 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 	.intr_conf = {
 		.lsc = 1, /**< lsc interrupt feature enabled */
diff --git a/examples/load_balancer/init.c b/examples/load_balancer/init.c
index f95e5ef848..ea4f6f407f 100644
--- a/examples/load_balancer/init.c
+++ b/examples/load_balancer/init.c
@@ -91,6 +91,7 @@ static struct rte_eth_conf port_conf = {
 		},
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 };
 
diff --git a/examples/multi_process/symmetric_mp/main.c b/examples/multi_process/symmetric_mp/main.c
index afbb3a4a2a..bfd253b944 100644
--- a/examples/multi_process/symmetric_mp/main.c
+++ b/examples/multi_process/symmetric_mp/main.c
@@ -273,6 +273,7 @@ smp_port_init(uint8_t port, struct rte_mempool *mbuf_pool, uint16_t num_queues)
 				},
 			},
 			.txmode = {
+				.mq_mode = ETH_DCB_NONE,
 			}
 	};
 	const uint16_t rx_rings = num_queues, tx_rings = num_queues;
diff --git a/examples/vmdq_dcb/main.c b/examples/vmdq_dcb/main.c
index 5d3efd2ccc..99d51e0257 100644
--- a/examples/vmdq_dcb/main.c
+++ b/examples/vmdq_dcb/main.c
@@ -130,6 +130,7 @@ static const struct rte_eth_conf vmdq_dcb_conf_default = {
 		.jumbo_frame    = 0, /**< Jumbo Frame Support disabled */
 	},
 	.txmode = {
+		.mq_mode = ETH_DCB_NONE,
 	},
 	.rx_adv_conf = {
 		/*
diff --git a/lib/librte_ether/rte_ethdev.c b/lib/librte_ether/rte_ethdev.c
index ac22f7a665..ab0fa59601 100644
--- a/lib/librte_ether/rte_ethdev.c
+++ b/lib/librte_ether/rte_ethdev.c
@@ -339,6 +339,66 @@ rte_eth_dev_configure(uint8_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,
 		    return (-EINVAL);
 		}
 	}
+	if (dev_conf->txmode.mq_mode == ETH_VMDQ_DCB_TX) {
+		const struct rte_eth_vmdq_dcb_tx_conf *conf;
+
+		if (nb_tx_q != ETH_VMDQ_DCB_NUM_QUEUES) {
+			PMD_DEBUG_TRACE("ethdev port_id=%d VMDQ+DCB, nb_tx_q "
+					"!= %d\n",
+					port_id, ETH_VMDQ_DCB_NUM_QUEUES);
+			return (-EINVAL);
+		}
+		conf = &(dev_conf->tx_adv_conf.vmdq_dcb_tx_conf);
+		if (! (conf->nb_queue_pools == ETH_16_POOLS ||
+		       conf->nb_queue_pools == ETH_32_POOLS)) {
+			PMD_DEBUG_TRACE("ethdev port_id=%d VMDQ+DCB selected, "
+				    "nb_queue_pools != %d or nb_queue_pools "
+				    "!= %d\n",
+				    port_id, ETH_16_POOLS, ETH_32_POOLS);
+			return (-EINVAL);
+		}
+	}
+	
+	/* For DCB mode check our configuration before we go further */
+	if (dev_conf->rxmode.mq_mode == ETH_DCB_RX) {
+		const struct rte_eth_dcb_rx_conf *conf;
+
+		if (nb_rx_q != ETH_DCB_NUM_QUEUES) {
+			PMD_DEBUG_TRACE("ethdev port_id=%d DCB, nb_rx_q "
+					"!= %d\n",
+					port_id, ETH_DCB_NUM_QUEUES);
+			return (-EINVAL);
+		}
+		conf = &(dev_conf->rx_adv_conf.dcb_rx_conf);
+		if (! (conf->nb_tcs == ETH_4_TCS ||
+		       conf->nb_tcs == ETH_8_TCS)) {
+			PMD_DEBUG_TRACE("ethdev port_id=%d DCB selected, "
+				    "nb_tcs != %d or nb_tcs "
+				    "!= %d\n",
+				    port_id, ETH_4_TCS, ETH_8_TCS);
+			return (-EINVAL);
+		}
+	}
+
+	if (dev_conf->txmode.mq_mode == ETH_DCB_TX) {
+		const struct rte_eth_dcb_tx_conf *conf;
+
+		if (nb_tx_q != ETH_DCB_NUM_QUEUES) {
+			PMD_DEBUG_TRACE("ethdev port_id=%d DCB, nb_tx_q "
+					"!= %d\n",
+					port_id, ETH_DCB_NUM_QUEUES);
+			return (-EINVAL);
+		}
+		conf = &(dev_conf->tx_adv_conf.dcb_tx_conf);
+		if (! (conf->nb_tcs == ETH_4_TCS ||
+		       conf->nb_tcs == ETH_8_TCS)) {
+			PMD_DEBUG_TRACE("ethdev port_id=%d DCB selected, "
+				    "nb_tcs != %d or nb_tcs "
+				    "!= %d\n",
+				    port_id, ETH_4_TCS, ETH_8_TCS);
+			return (-EINVAL);
+		}
+	}
 
 	diag = (*dev->dev_ops->dev_configure)(dev, nb_rx_q, nb_tx_q);
 	if (diag != 0) {
diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h
index afcd240e75..9e3ac32b33 100644
--- a/lib/librte_ether/rte_ethdev.h
+++ b/lib/librte_ether/rte_ethdev.h
@@ -240,7 +240,18 @@ struct rte_eth_thresh {
  */
 enum rte_eth_rx_mq_mode {
 	ETH_RSS     = 0,     /**< Default to RSS mode */
-	ETH_VMDQ_DCB         /**< Use VMDQ+DCB to route traffic to queues */
+	ETH_VMDQ_DCB,        /**< Use VMDQ+DCB to route traffic to queues */
+	ETH_DCB_RX           /**< For RX side,only DCB is on. */
+};
+
+/**
+ * A set of values to identify what method is to be used to transmit 
+ * packets using multi-TCs.
+ */
+enum rte_eth_tx_mq_mode {
+	ETH_DCB_NONE    = 0, 	/**< It is not in DCB mode. */
+	ETH_VMDQ_DCB_TX,	/**< For TX side,both DCB and VT is on. */
+	ETH_DCB_TX           	/**< For TX side,only DCB is on. */
 };
 
 /**
@@ -290,6 +301,20 @@ struct rte_eth_rss_conf {
 #define ETH_VMDQ_MAX_VLAN_FILTERS   64 /**< Maximum nb. of VMDQ vlan filters. */
 #define ETH_DCB_NUM_USER_PRIORITIES 8  /**< Maximum nb. of DCB priorities. */
 #define ETH_VMDQ_DCB_NUM_QUEUES     128 /**< Maximum nb. of VMDQ DCB queues. */
+#define ETH_DCB_NUM_QUEUES          128 /**< Maximum nb. of DCB queues. */
+
+/* DCB capability defines */
+#define ETH_DCB_PG_SUPPORT      0x00000001 /**< Priority Group(ETS) support. */
+#define ETH_DCB_PFC_SUPPORT     0x00000002 /**< Priority Flow Control support. */ 
+
+/**
+ * This enum indicates the possible number of traffic classes
+ * in DCB configratioins
+ */
+enum rte_eth_nb_tcs {
+	ETH_4_TCS = 4, /**< 4 TCs with DCB. */
+	ETH_8_TCS = 8  /**< 8 TCs with DCB. */
+};
 
 /**
  * This enum indicates the possible number of queue pools
@@ -300,6 +325,25 @@ enum rte_eth_nb_pools {
 	ETH_32_POOLS = 32  /**< 32 pools with DCB. */
 };
 
+/* This structure may be extended in future. */
+struct rte_eth_dcb_rx_conf {
+	enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs */
+	uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
+	/**< Possible DCB queue,4 or 8. */
+};
+ 
+struct rte_eth_vmdq_dcb_tx_conf {
+	enum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools. */
+	uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
+	/**< Possible DCB queue,4 or 8. */
+};
+ 
+struct rte_eth_dcb_tx_conf {
+	enum rte_eth_nb_tcs nb_tcs; /**< possible DCB TCs, 4 or 8 TCs. */
+	uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
+	/**< Possible DCB queue,4 or 8. */
+};
+
 /**
  * A structure used to configure the VMDQ+DCB feature
  * of an Ethernet port.
@@ -326,9 +370,9 @@ struct rte_eth_vmdq_dcb_conf {
 
 /**
  * A structure used to configure the TX features of an Ethernet port.
- * For future extensions.
  */
 struct rte_eth_txmode {
+	enum rte_eth_tx_mq_mode mq_mode; /**< TX multi-queues mode. */
 };
 
 /**
@@ -538,7 +582,18 @@ struct rte_eth_conf {
 		struct rte_eth_rss_conf rss_conf; /**< Port RSS configuration */
 		struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf;
 		/**< Port vmdq+dcb configuration. */
+		struct rte_eth_dcb_rx_conf dcb_rx_conf;
+		/**< Port dcb RX configuration. */
 	} rx_adv_conf; /**< Port RX filtering configuration (union). */
+	union {
+		struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf;
+		/**< Port vmdq+dcb TX configuration. */
+		struct rte_eth_dcb_tx_conf dcb_tx_conf;
+		/**< Port dcb TX configuration. */
+	} tx_adv_conf; /**< Port TX DCB configuration (union). */
+	/** Currently,Priority Flow Control(PFC) are supported,if DCB with PFC 
+ 	    is needed,and the variable must be set ETH_DCB_PFC_SUPPORT. */ 
+	uint32_t dcb_capability_en; 
 	struct rte_fdir_conf fdir_conf; /**< FDIR configuration. */
 	struct rte_intr_conf intr_conf; /**< Interrupt mode configuration. */
 };