From: Radu Nicolau Date: Wed, 23 Sep 2020 14:22:51 +0000 (+0000) Subject: common/qat: use write combining store for tail updates X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=0767e9eba1fb703f9376ae9037b6237cb74c8541;p=dpdk.git common/qat: use write combining store for tail updates Performance improvement: use a write combining store instead of a regular mmio write to update queue tail registers. Signed-off-by: Radu Nicolau Acked-by: Fiona Trahe --- diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index d9edbcdbd7..1002f416e5 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -103,6 +103,10 @@ New Features Updated the Intel i40e driver to use write combining stores. +* **Updated Intel qat driver.** + + Updated the Intel qat driver to use write combining stores. + * **Added Ice Lake (Gen4) support for Intel NTB.** Added NTB device support (4th generation) for Intel Ice Lake platform. diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h index 1eef5513fb..504ffb7236 100644 --- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h +++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h @@ -9,6 +9,8 @@ /* CSR write macro */ #define ADF_CSR_WR(csrAddr, csrOffset, val) \ rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) +#define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \ + rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset)) /* CSR read macro */ #define ADF_CSR_RD(csrAddr, csrOffset) \ @@ -110,10 +112,10 @@ do { \ ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \ } while (0) #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ - ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ + ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ ADF_RING_CSR_RING_HEAD + (ring << 2), value) #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ - ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ + ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ ADF_RING_CSR_RING_TAIL + (ring << 2), value) #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ do { \