From: Qiming Yang Date: Wed, 16 Oct 2019 18:33:53 +0000 (+0800) Subject: net/ice: add devargs to control pipeline mode X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=0998c89a856410881378a15f268f18a7c65e02ed;p=dpdk.git net/ice: add devargs to control pipeline mode Added a devarg to control the mode in generic flow API. We use none-pipeline mode by default. Signed-off-by: Qiming Yang Acked-by: Qi Zhang Reviewed-by: Xiaolong Ye --- diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst index 641f34840b..933f634803 100644 --- a/doc/guides/nics/ice.rst +++ b/doc/guides/nics/ice.rst @@ -61,6 +61,25 @@ Runtime Config Options NOTE: In Safe mode, only very limited features are available, features like RSS, checksum, fdir, tunneling ... are all disabled. +- ``Generic Flow Pipeline Mode Support`` (default ``0``) + + In pipeline mode, a flow can be set at one specific stage by setting parameter + ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with + priority 0 located at the first pipeline stage which typically be used as a firewall + to drop the packet on a blacklist(we called it permission stage). At this stage, + flow rules are created for the device's exact match engine: switch. Flows with priority + !0 located at the second stage, typically packets are classified here and be steered to + specific queue or queue group (we called it distribution stage), At this stage, flow + rules are created for device's flow director engine. + For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director + rule or a switch rule depends on its pattern/action and the resource allocation situation, + all flows are virtually at the same pipeline stage. + By default, generic flow API is enabled in none-pipeline mode, user can choose to + use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``, + for example:: + + -w 80:00.0,pipeline-mode-support=1 + - ``Protocol extraction for per queue`` Configure the RX queues to do protocol extraction into ``rte_mbuf::udata64`` diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst index f046bffb9e..5f63ae42e7 100644 --- a/doc/guides/rel_notes/release_19_11.rst +++ b/doc/guides/rel_notes/release_19_11.rst @@ -114,6 +114,8 @@ New Features * Added support for handling Receive Flex Descriptor. * Added support for protocol extraction on per Rx queue. * Added support for the ``RTE_ETH_DEV_CLOSE_REMOVE`` flag. + * Generic filter enhancement + - Supported pipeline mode. * **Added cryptodev asymmetric session-less operation.** diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 5567beb55a..c6bfcdb74b 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -19,10 +19,12 @@ /* devargs */ #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" +#define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" #define ICE_PROTO_XTR_ARG "proto_xtr" static const char * const ice_valid_args[] = { ICE_SAFE_MODE_SUPPORT_ARG, + ICE_PIPELINE_MODE_SUPPORT_ARG, ICE_PROTO_XTR_ARG, NULL }; @@ -1833,6 +1835,11 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, &parse_bool, &ad->devargs.safe_mode_support); + if (ret) + goto bail; + + ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, + &parse_bool, &ad->devargs.pipe_mode_support); bail: rte_kvargs_free(kvlist); @@ -4298,7 +4305,8 @@ RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ice, ICE_PROTO_XTR_ARG "=[queue:]" - ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"); + ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" + ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); RTE_INIT(ice_init_log) { diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 2fd98817bd..6790f64d40 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -289,6 +289,7 @@ struct ice_pf { struct ice_devargs { int safe_mode_support; uint8_t proto_xtr_dflt; + int pipe_mode_support; uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; };