From: Nithin Dabilpuram Date: Fri, 21 Jan 2022 12:04:15 +0000 (+0530) Subject: common/cnxk: fix shift offset for TL3 length disable X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=132dac7536e9bb2be9d9edabc1752dca7b25279a;p=dpdk.git common/cnxk: fix shift offset for TL3 length disable Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE register to be 24 instead of zero similar to other level SHAPE registers. Also mask unused bits in adjust value. Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram Signed-off-by: Satha Rao --- diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 543adf9e56..9e80c2a5fe 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -642,6 +642,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node, else if (profile) adjust = profile->pkt_len_adj; + adjust &= 0x1FF; plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, " "pir %" PRIu64 "(%" PRIu64 "B)," " cir %" PRIu64 "(%" PRIu64 "B)" @@ -708,7 +709,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node, /* Configure RED algo */ reg[k] = NIX_AF_TL3X_SHAPE(schq); regval[k] = (adjust | (uint64_t)node->red_algo << 9 | - (uint64_t)node->pkt_mode); + (uint64_t)node->pkt_mode << 24); k++; break;