From: Yongseok Koh Date: Mon, 9 Oct 2017 18:46:58 +0000 (-0700) Subject: net/mlx5: match Rx completion entry size to cacheline X-Git-Tag: spdx-start~1499 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=161b93e5e7d0482c0d7e77603c2406acdfc94088;p=dpdk.git net/mlx5: match Rx completion entry size to cacheline The size of Rx completion entry should match the size of a cacheline. This is already reflected in struct mlx5_cqe by adding 64bytes padding if a cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline. Signed-off-by: Yongseok Koh Acked-by: Nelio Laranjeiro --- diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index b2087c0adf..e1aa9b914f 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1012,6 +1012,9 @@ rte_mlx5_pmd_init(void) setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); /* Don't map UAR to WC if BlueFlame is not used.*/ setenv("MLX5_SHUT_UP_BF", "1", 1); + /* Match the size of Rx completion entry to the size of a cacheline. */ + if (RTE_CACHE_LINE_SIZE == 128) + setenv("MLX5_CQE_SIZE", "128", 0); ibv_fork_init(); rte_pci_register(&mlx5_driver); }