From: Chao Zhu Date: Wed, 30 Mar 2016 15:39:17 +0000 (+0800) Subject: eal/ppc: fix prefetch instruction X-Git-Tag: spdx-start~7108 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=1861116ee67143762e9ce37b3525f97bbbe16da2;p=dpdk.git eal/ppc: fix prefetch instruction Current prefetch instruction (dcbt) implementation for IBM POWER8 has wrong Touch Hint(TH) parameter. The current setting of TH=1 indicates to load data from current cache line and an unlimited number of sequentially following cache lines. TTH=0 means to load data from current cache line. rte_prefetch0 function is defined to load one cache line, which means TH=0 is suited here. Signed-off-by: Chao Zhu --- diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h index bcc7185c2b..9a1995eaaa 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h @@ -41,17 +41,17 @@ extern "C" { static inline void rte_prefetch0(const volatile void *p) { - asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); + asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p)); } static inline void rte_prefetch1(const volatile void *p) { - asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); + asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p)); } static inline void rte_prefetch2(const volatile void *p) { - asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); + asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p)); } static inline void rte_prefetch_non_temporal(const volatile void *p)