From: Honnappa Nagarahalli Date: Mon, 6 Jul 2020 23:43:31 +0000 (-0500) Subject: eal/arm: adjust memory barriers for IO on ARMv8 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=264f7f80e19fcba74637cd89561ea36bee0b0839;p=dpdk.git eal/arm: adjust memory barriers for IO on ARMv8 Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy atomicity memory model. Armv8-a memory model has been strengthened to require other-multi-copy atomicity. This property requires memory accesses from an observer to become visible to all other observers simultaneously [3]. This means a) A write arriving at an endpoint shared between multiple CPUs is visible to all CPUs b) A write that is visible to all CPUs is also visible to all other observers in the shareability domain This allows for using cheaper DMB instructions in the place of DSB for devices that are visible to all CPUs (i.e. devices that DPDK caters to). Please refer to [1], [2] and [3] for more information. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f [2] https://www.youtube.com/watch?v=i6DayghhA8Q [3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/ Signed-off-by: Honnappa Nagarahalli Acked-by: Jerin Jacob Tested-by: Ruifeng Wang --- diff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst index c3c39ca356..f45d378d43 100644 --- a/doc/guides/rel_notes/release_20_08.rst +++ b/doc/guides/rel_notes/release_20_08.rst @@ -56,6 +56,13 @@ New Features Also, make sure to start the actual text at the margin. ========================================================= +* **rte_*mb APIs are updated to use DMB instruction for ARMv8.** + + ARMv8 memory model has been strengthened to require other-multi-copy + atomicity. This allows for using DMB instruction instead of DSB for IO + barriers. rte_*mb APIs, for ARMv8 platforms, are changed to use DMB + instruction to reflect this. + * **Added the support for vfio-pci new VF token interface.** From Linux 5.7, vfio-pci supports to bind both SR-IOV PF and the created VFs, diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h index 7b7099cdc1..e42f69edce 100644 --- a/lib/librte_eal/arm/include/rte_atomic_64.h +++ b/lib/librte_eal/arm/include/rte_atomic_64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2015 Cavium, Inc - * Copyright(c) 2019 Arm Limited + * Copyright(c) 2020 Arm Limited */ #ifndef _RTE_ATOMIC_ARM64_H_ @@ -19,11 +19,11 @@ extern "C" { #include #include -#define rte_mb() asm volatile("dsb sy" : : : "memory") +#define rte_mb() asm volatile("dmb osh" : : : "memory") -#define rte_wmb() asm volatile("dsb st" : : : "memory") +#define rte_wmb() asm volatile("dmb oshst" : : : "memory") -#define rte_rmb() asm volatile("dsb ld" : : : "memory") +#define rte_rmb() asm volatile("dmb oshld" : : : "memory") #define rte_smp_mb() asm volatile("dmb ish" : : : "memory") @@ -37,9 +37,9 @@ extern "C" { #define rte_io_rmb() rte_rmb() -#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory") +#define rte_cio_wmb() rte_wmb() -#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") +#define rte_cio_rmb() rte_rmb() /*------------------------ 128 bit atomic operations -------------------------*/