From: Thomas Monjalon Date: Fri, 27 Mar 2020 01:15:35 +0000 (+0100) Subject: eal: move arch-specific C files X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=2a1991799ea11c9fe10cffd3f25f06a418e37f35;p=dpdk.git eal: move arch-specific C files The arch-specific directories arm, ppc and x86 in common/arch/ are moved at the same level as the OS-specific directories. It makes more clear that EAL is covering a matrix combining OS and arch. Signed-off-by: Thomas Monjalon Reviewed-by: David Christensen Acked-by: David Marchand --- diff --git a/MAINTAINERS b/MAINTAINERS index a3f1a53c4e..b373efc578 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -261,7 +261,7 @@ F: app/test/test_rand_perf.c ARM v7 M: Jan Viktorin M: Gavin Hu -F: lib/librte_eal/common/arch/arm/ +F: lib/librte_eal/arm/ F: lib/librte_eal/common/include/arch/arm/ ARM v8 @@ -281,7 +281,7 @@ F: drivers/net/virtio/virtio_rxtx_simple_neon.c IBM POWER (alpha) M: David Christensen -F: lib/librte_eal/common/arch/ppc_64/ +F: lib/librte_eal/ppc/ F: lib/librte_eal/common/include/arch/ppc_64/ F: drivers/net/i40e/i40e_rxtx_vec_altivec.c F: examples/l3fwd/*altivec.h @@ -289,7 +289,7 @@ F: examples/l3fwd/*altivec.h Intel x86 M: Bruce Richardson M: Konstantin Ananyev -F: lib/librte_eal/common/arch/x86/ +F: lib/librte_eal/x86/ F: lib/librte_eal/common/include/arch/x86/ Linux EAL (with overlaps) diff --git a/devtools/build-tags.sh b/devtools/build-tags.sh index dc037f92b3..8221f90f70 100755 --- a/devtools/build-tags.sh +++ b/devtools/build-tags.sh @@ -79,7 +79,7 @@ bsd_sources() arm_common() { - find_sources "lib/librte_eal/common/arch/arm" '*.[chS]' + find_sources "lib/librte_eal/arm" '*.[chS]' find_sources "$source_dirs" '*neon*.[chS]' } @@ -100,8 +100,7 @@ arm_64_sources() x86_common() { - find_sources "lib/librte_eal/common/arch/x86" '*.[chS]' - + find_sources "lib/librte_eal/x86" '*.[chS]' find_sources "examples/performance-thread/common/arch/x86" '*.[chS]' find_sources "$source_dirs" '*_sse*.[chS]' find_sources "$source_dirs" '*_avx*.[chS]' @@ -124,7 +123,7 @@ x86_64_sources() ppc_64_sources() { - find_sources "lib/librte_eal/common/arch/ppc_64" '*.[chS]' + find_sources "lib/librte_eal/ppc" '*.[chS]' find_sources "lib/librte_eal/common/include/arch/ppc_64" '*.[chS]' find_sources "$source_dirs" '*altivec*.[chS]' } diff --git a/lib/librte_eal/arm/meson.build b/lib/librte_eal/arm/meson.build new file mode 100644 index 0000000000..f8f7dea9b2 --- /dev/null +++ b/lib/librte_eal/arm/meson.build @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation. + +sources += files( + 'rte_cpuflags.c', + 'rte_cycles.c', + 'rte_hypervisor.c', +) diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c new file mode 100644 index 0000000000..caf3dc83a5 --- /dev/null +++ b/lib/librte_eal/arm/rte_cpuflags.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) Cavium, Inc. 2015. + * Copyright(c) 2015 RehiveTech. All rights reserved. + */ + +#include "rte_cpuflags.h" + +#include +#include +#include +#include +#include + +#ifndef AT_HWCAP +#define AT_HWCAP 16 +#endif + +#ifndef AT_HWCAP2 +#define AT_HWCAP2 26 +#endif + +#ifndef AT_PLATFORM +#define AT_PLATFORM 15 +#endif + +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_HWCAP2, + REG_PLATFORM, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +/** + * Struct to hold a processor feature entry + */ +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +#ifdef RTE_ARCH_ARMv7 +#define PLATFORM_STR "v7l" +typedef Elf32_auxv_t _Elfx_auxv_t; + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(SWP, REG_HWCAP, 0) + FEAT_DEF(HALF, REG_HWCAP, 1) + FEAT_DEF(THUMB, REG_HWCAP, 2) + FEAT_DEF(A26BIT, REG_HWCAP, 3) + FEAT_DEF(FAST_MULT, REG_HWCAP, 4) + FEAT_DEF(FPA, REG_HWCAP, 5) + FEAT_DEF(VFP, REG_HWCAP, 6) + FEAT_DEF(EDSP, REG_HWCAP, 7) + FEAT_DEF(JAVA, REG_HWCAP, 8) + FEAT_DEF(IWMMXT, REG_HWCAP, 9) + FEAT_DEF(CRUNCH, REG_HWCAP, 10) + FEAT_DEF(THUMBEE, REG_HWCAP, 11) + FEAT_DEF(NEON, REG_HWCAP, 12) + FEAT_DEF(VFPv3, REG_HWCAP, 13) + FEAT_DEF(VFPv3D16, REG_HWCAP, 14) + FEAT_DEF(TLS, REG_HWCAP, 15) + FEAT_DEF(VFPv4, REG_HWCAP, 16) + FEAT_DEF(IDIVA, REG_HWCAP, 17) + FEAT_DEF(IDIVT, REG_HWCAP, 18) + FEAT_DEF(VFPD32, REG_HWCAP, 19) + FEAT_DEF(LPAE, REG_HWCAP, 20) + FEAT_DEF(EVTSTRM, REG_HWCAP, 21) + FEAT_DEF(AES, REG_HWCAP2, 0) + FEAT_DEF(PMULL, REG_HWCAP2, 1) + FEAT_DEF(SHA1, REG_HWCAP2, 2) + FEAT_DEF(SHA2, REG_HWCAP2, 3) + FEAT_DEF(CRC32, REG_HWCAP2, 4) + FEAT_DEF(V7L, REG_PLATFORM, 0) +}; + +#elif defined RTE_ARCH_ARM64 +#define PLATFORM_STR "aarch64" +typedef Elf64_auxv_t _Elfx_auxv_t; + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(FP, REG_HWCAP, 0) + FEAT_DEF(NEON, REG_HWCAP, 1) + FEAT_DEF(EVTSTRM, REG_HWCAP, 2) + FEAT_DEF(AES, REG_HWCAP, 3) + FEAT_DEF(PMULL, REG_HWCAP, 4) + FEAT_DEF(SHA1, REG_HWCAP, 5) + FEAT_DEF(SHA2, REG_HWCAP, 6) + FEAT_DEF(CRC32, REG_HWCAP, 7) + FEAT_DEF(ATOMICS, REG_HWCAP, 8) + FEAT_DEF(AARCH64, REG_PLATFORM, 1) +}; +#endif /* RTE_ARCH */ + +/* + * Read AUXV software register and get cpu features for ARM + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); + out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); + if (!rte_cpu_strcmp_auxval(AT_PLATFORM, PLATFORM_STR)) + out[REG_PLATFORM] = 0x0001; +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} diff --git a/lib/librte_eal/arm/rte_cycles.c b/lib/librte_eal/arm/rte_cycles.c new file mode 100644 index 0000000000..3500d523ef --- /dev/null +++ b/lib/librte_eal/arm/rte_cycles.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 Cavium, Inc + */ + +#include "eal_private.h" + +uint64_t +get_tsc_freq_arch(void) +{ +#if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU + uint64_t freq; + asm volatile("mrs %0, cntfrq_el0" : "=r" (freq)); + return freq; +#else + return 0; +#endif +} diff --git a/lib/librte_eal/arm/rte_hypervisor.c b/lib/librte_eal/arm/rte_hypervisor.c new file mode 100644 index 0000000000..08a1c97d10 --- /dev/null +++ b/lib/librte_eal/arm/rte_hypervisor.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2017 Mellanox Technologies, Ltd + */ + +#include "rte_hypervisor.h" + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + return RTE_HYPERVISOR_UNKNOWN; +} diff --git a/lib/librte_eal/common/arch/arm/meson.build b/lib/librte_eal/common/arch/arm/meson.build deleted file mode 100644 index 79731e1a2c..0000000000 --- a/lib/librte_eal/common/arch/arm/meson.build +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2017 Intel Corporation. - -eal_common_arch_sources = files('rte_cpuflags.c', - 'rte_cycles.c', 'rte_hypervisor.c') diff --git a/lib/librte_eal/common/arch/arm/rte_cpuflags.c b/lib/librte_eal/common/arch/arm/rte_cpuflags.c deleted file mode 100644 index caf3dc83a5..0000000000 --- a/lib/librte_eal/common/arch/arm/rte_cpuflags.c +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) Cavium, Inc. 2015. - * Copyright(c) 2015 RehiveTech. All rights reserved. - */ - -#include "rte_cpuflags.h" - -#include -#include -#include -#include -#include - -#ifndef AT_HWCAP -#define AT_HWCAP 16 -#endif - -#ifndef AT_HWCAP2 -#define AT_HWCAP2 26 -#endif - -#ifndef AT_PLATFORM -#define AT_PLATFORM 15 -#endif - -enum cpu_register_t { - REG_NONE = 0, - REG_HWCAP, - REG_HWCAP2, - REG_PLATFORM, - REG_MAX -}; - -typedef uint32_t hwcap_registers_t[REG_MAX]; - -/** - * Struct to hold a processor feature entry - */ -struct feature_entry { - uint32_t reg; - uint32_t bit; -#define CPU_FLAG_NAME_MAX_LEN 64 - char name[CPU_FLAG_NAME_MAX_LEN]; -}; - -#define FEAT_DEF(name, reg, bit) \ - [RTE_CPUFLAG_##name] = {reg, bit, #name}, - -#ifdef RTE_ARCH_ARMv7 -#define PLATFORM_STR "v7l" -typedef Elf32_auxv_t _Elfx_auxv_t; - -const struct feature_entry rte_cpu_feature_table[] = { - FEAT_DEF(SWP, REG_HWCAP, 0) - FEAT_DEF(HALF, REG_HWCAP, 1) - FEAT_DEF(THUMB, REG_HWCAP, 2) - FEAT_DEF(A26BIT, REG_HWCAP, 3) - FEAT_DEF(FAST_MULT, REG_HWCAP, 4) - FEAT_DEF(FPA, REG_HWCAP, 5) - FEAT_DEF(VFP, REG_HWCAP, 6) - FEAT_DEF(EDSP, REG_HWCAP, 7) - FEAT_DEF(JAVA, REG_HWCAP, 8) - FEAT_DEF(IWMMXT, REG_HWCAP, 9) - FEAT_DEF(CRUNCH, REG_HWCAP, 10) - FEAT_DEF(THUMBEE, REG_HWCAP, 11) - FEAT_DEF(NEON, REG_HWCAP, 12) - FEAT_DEF(VFPv3, REG_HWCAP, 13) - FEAT_DEF(VFPv3D16, REG_HWCAP, 14) - FEAT_DEF(TLS, REG_HWCAP, 15) - FEAT_DEF(VFPv4, REG_HWCAP, 16) - FEAT_DEF(IDIVA, REG_HWCAP, 17) - FEAT_DEF(IDIVT, REG_HWCAP, 18) - FEAT_DEF(VFPD32, REG_HWCAP, 19) - FEAT_DEF(LPAE, REG_HWCAP, 20) - FEAT_DEF(EVTSTRM, REG_HWCAP, 21) - FEAT_DEF(AES, REG_HWCAP2, 0) - FEAT_DEF(PMULL, REG_HWCAP2, 1) - FEAT_DEF(SHA1, REG_HWCAP2, 2) - FEAT_DEF(SHA2, REG_HWCAP2, 3) - FEAT_DEF(CRC32, REG_HWCAP2, 4) - FEAT_DEF(V7L, REG_PLATFORM, 0) -}; - -#elif defined RTE_ARCH_ARM64 -#define PLATFORM_STR "aarch64" -typedef Elf64_auxv_t _Elfx_auxv_t; - -const struct feature_entry rte_cpu_feature_table[] = { - FEAT_DEF(FP, REG_HWCAP, 0) - FEAT_DEF(NEON, REG_HWCAP, 1) - FEAT_DEF(EVTSTRM, REG_HWCAP, 2) - FEAT_DEF(AES, REG_HWCAP, 3) - FEAT_DEF(PMULL, REG_HWCAP, 4) - FEAT_DEF(SHA1, REG_HWCAP, 5) - FEAT_DEF(SHA2, REG_HWCAP, 6) - FEAT_DEF(CRC32, REG_HWCAP, 7) - FEAT_DEF(ATOMICS, REG_HWCAP, 8) - FEAT_DEF(AARCH64, REG_PLATFORM, 1) -}; -#endif /* RTE_ARCH */ - -/* - * Read AUXV software register and get cpu features for ARM - */ -static void -rte_cpu_get_features(hwcap_registers_t out) -{ - out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); - out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); - if (!rte_cpu_strcmp_auxval(AT_PLATFORM, PLATFORM_STR)) - out[REG_PLATFORM] = 0x0001; -} - -/* - * Checks if a particular flag is available on current machine. - */ -int -rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) -{ - const struct feature_entry *feat; - hwcap_registers_t regs = {0}; - - if (feature >= RTE_CPUFLAG_NUMFLAGS) - return -ENOENT; - - feat = &rte_cpu_feature_table[feature]; - if (feat->reg == REG_NONE) - return -EFAULT; - - rte_cpu_get_features(regs); - return (regs[feat->reg] >> feat->bit) & 1; -} - -const char * -rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) -{ - if (feature >= RTE_CPUFLAG_NUMFLAGS) - return NULL; - return rte_cpu_feature_table[feature].name; -} diff --git a/lib/librte_eal/common/arch/arm/rte_cycles.c b/lib/librte_eal/common/arch/arm/rte_cycles.c deleted file mode 100644 index 3500d523ef..0000000000 --- a/lib/librte_eal/common/arch/arm/rte_cycles.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2015 Cavium, Inc - */ - -#include "eal_private.h" - -uint64_t -get_tsc_freq_arch(void) -{ -#if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU - uint64_t freq; - asm volatile("mrs %0, cntfrq_el0" : "=r" (freq)); - return freq; -#else - return 0; -#endif -} diff --git a/lib/librte_eal/common/arch/arm/rte_hypervisor.c b/lib/librte_eal/common/arch/arm/rte_hypervisor.c deleted file mode 100644 index 08a1c97d10..0000000000 --- a/lib/librte_eal/common/arch/arm/rte_hypervisor.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2017 Mellanox Technologies, Ltd - */ - -#include "rte_hypervisor.h" - -enum rte_hypervisor -rte_hypervisor_get(void) -{ - return RTE_HYPERVISOR_UNKNOWN; -} diff --git a/lib/librte_eal/common/arch/ppc b/lib/librte_eal/common/arch/ppc deleted file mode 120000 index 2db6a0c918..0000000000 --- a/lib/librte_eal/common/arch/ppc +++ /dev/null @@ -1 +0,0 @@ -ppc_64 \ No newline at end of file diff --git a/lib/librte_eal/common/arch/ppc_64/meson.build b/lib/librte_eal/common/arch/ppc_64/meson.build deleted file mode 100644 index 40b3dc533a..0000000000 --- a/lib/librte_eal/common/arch/ppc_64/meson.build +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2018 Luca Boccassi - -eal_common_arch_sources = files('rte_cpuflags.c', - 'rte_cycles.c', 'rte_hypervisor.c') diff --git a/lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c b/lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c deleted file mode 100644 index 3bb7563ce9..0000000000 --- a/lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) IBM Corporation 2014. - */ - -#include "rte_cpuflags.h" - -#include -#include -#include -#include - -/* Symbolic values for the entries in the auxiliary table */ -#define AT_HWCAP 16 -#define AT_HWCAP2 26 - -/* software based registers */ -enum cpu_register_t { - REG_NONE = 0, - REG_HWCAP, - REG_HWCAP2, - REG_MAX -}; - -typedef uint32_t hwcap_registers_t[REG_MAX]; - -struct feature_entry { - uint32_t reg; - uint32_t bit; -#define CPU_FLAG_NAME_MAX_LEN 64 - char name[CPU_FLAG_NAME_MAX_LEN]; -}; - -#define FEAT_DEF(name, reg, bit) \ - [RTE_CPUFLAG_##name] = {reg, bit, #name}, - -const struct feature_entry rte_cpu_feature_table[] = { - FEAT_DEF(PPC_LE, REG_HWCAP, 0) - FEAT_DEF(TRUE_LE, REG_HWCAP, 1) - FEAT_DEF(PSERIES_PERFMON_COMPAT, REG_HWCAP, 6) - FEAT_DEF(VSX, REG_HWCAP, 7) - FEAT_DEF(ARCH_2_06, REG_HWCAP, 8) - FEAT_DEF(POWER6_EXT, REG_HWCAP, 9) - FEAT_DEF(DFP, REG_HWCAP, 10) - FEAT_DEF(PA6T, REG_HWCAP, 11) - FEAT_DEF(ARCH_2_05, REG_HWCAP, 12) - FEAT_DEF(ICACHE_SNOOP, REG_HWCAP, 13) - FEAT_DEF(SMT, REG_HWCAP, 14) - FEAT_DEF(BOOKE, REG_HWCAP, 15) - FEAT_DEF(CELLBE, REG_HWCAP, 16) - FEAT_DEF(POWER5_PLUS, REG_HWCAP, 17) - FEAT_DEF(POWER5, REG_HWCAP, 18) - FEAT_DEF(POWER4, REG_HWCAP, 19) - FEAT_DEF(NOTB, REG_HWCAP, 20) - FEAT_DEF(EFP_DOUBLE, REG_HWCAP, 21) - FEAT_DEF(EFP_SINGLE, REG_HWCAP, 22) - FEAT_DEF(SPE, REG_HWCAP, 23) - FEAT_DEF(UNIFIED_CACHE, REG_HWCAP, 24) - FEAT_DEF(4xxMAC, REG_HWCAP, 25) - FEAT_DEF(MMU, REG_HWCAP, 26) - FEAT_DEF(FPU, REG_HWCAP, 27) - FEAT_DEF(ALTIVEC, REG_HWCAP, 28) - FEAT_DEF(PPC601, REG_HWCAP, 29) - FEAT_DEF(PPC64, REG_HWCAP, 30) - FEAT_DEF(PPC32, REG_HWCAP, 31) - FEAT_DEF(TAR, REG_HWCAP2, 26) - FEAT_DEF(LSEL, REG_HWCAP2, 27) - FEAT_DEF(EBB, REG_HWCAP2, 28) - FEAT_DEF(DSCR, REG_HWCAP2, 29) - FEAT_DEF(HTM, REG_HWCAP2, 30) - FEAT_DEF(ARCH_2_07, REG_HWCAP2, 31) -}; - -/* - * Read AUXV software register and get cpu features for Power - */ -static void -rte_cpu_get_features(hwcap_registers_t out) -{ - out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); - out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); -} - -/* - * Checks if a particular flag is available on current machine. - */ -int -rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) -{ - const struct feature_entry *feat; - hwcap_registers_t regs = {0}; - - if (feature >= RTE_CPUFLAG_NUMFLAGS) - return -ENOENT; - - feat = &rte_cpu_feature_table[feature]; - if (feat->reg == REG_NONE) - return -EFAULT; - - rte_cpu_get_features(regs); - return (regs[feat->reg] >> feat->bit) & 1; -} - -const char * -rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) -{ - if (feature >= RTE_CPUFLAG_NUMFLAGS) - return NULL; - return rte_cpu_feature_table[feature].name; -} diff --git a/lib/librte_eal/common/arch/ppc_64/rte_cycles.c b/lib/librte_eal/common/arch/ppc_64/rte_cycles.c deleted file mode 100644 index c96a2143b3..0000000000 --- a/lib/librte_eal/common/arch/ppc_64/rte_cycles.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) IBM Corporation 2019. - */ - -#include "eal_private.h" - -uint64_t -get_tsc_freq_arch(void) -{ - return 0; -} diff --git a/lib/librte_eal/common/arch/ppc_64/rte_hypervisor.c b/lib/librte_eal/common/arch/ppc_64/rte_hypervisor.c deleted file mode 100644 index 08a1c97d10..0000000000 --- a/lib/librte_eal/common/arch/ppc_64/rte_hypervisor.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2017 Mellanox Technologies, Ltd - */ - -#include "rte_hypervisor.h" - -enum rte_hypervisor -rte_hypervisor_get(void) -{ - return RTE_HYPERVISOR_UNKNOWN; -} diff --git a/lib/librte_eal/common/arch/x86/meson.build b/lib/librte_eal/common/arch/x86/meson.build deleted file mode 100644 index 14bf204c6f..0000000000 --- a/lib/librte_eal/common/arch/x86/meson.build +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2017 Intel Corporation - -eal_common_arch_sources = files('rte_spinlock.c', 'rte_cpuflags.c', - 'rte_cycles.c', 'rte_hypervisor.c') diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c deleted file mode 100644 index 6492df556c..0000000000 --- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2010-2015 Intel Corporation - */ - -#include "rte_cpuflags.h" - -#include -#include -#include - -#include "rte_cpuid.h" - -/** - * Struct to hold a processor feature entry - */ -struct feature_entry { - uint32_t leaf; /**< cpuid leaf */ - uint32_t subleaf; /**< cpuid subleaf */ - uint32_t reg; /**< cpuid register */ - uint32_t bit; /**< cpuid register bit */ -#define CPU_FLAG_NAME_MAX_LEN 64 - char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */ -}; - -#define FEAT_DEF(name, leaf, subleaf, reg, bit) \ - [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name }, - -const struct feature_entry rte_cpu_feature_table[] = { - FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0) - FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1) - FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2) - FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3) - FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4) - FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5) - FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6) - FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7) - FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8) - FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9) - FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10) - FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12) - FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13) - FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14) - FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15) - FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17) - FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18) - FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19) - FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20) - FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21) - FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22) - FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23) - FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24) - FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25) - FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26) - FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27) - FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28) - FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29) - FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30) - FEAT_DEF(HYPERVISOR, 0x00000001, 0, RTE_REG_ECX, 31) - - FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0) - FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1) - FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2) - FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3) - FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4) - FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5) - FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6) - FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7) - FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8) - FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9) - FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11) - FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12) - FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13) - FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14) - FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15) - FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16) - FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17) - FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18) - FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19) - FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21) - FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22) - FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23) - FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24) - FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25) - FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26) - FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27) - FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28) - FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29) - FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31) - - FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0) - FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1) - FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2) - FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4) - FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5) - FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6) - - FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0) - FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1) - FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3) - - FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0) - FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2) - FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4) - FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5) - FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6) - FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7) - FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) - FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) - FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) - FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) - FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18) - - FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) - FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) - - FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11) - FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20) - FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26) - FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27) - FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) - - FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) -}; - -int -rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) -{ - const struct feature_entry *feat; - cpuid_registers_t regs; - unsigned int maxleaf; - - if (feature >= RTE_CPUFLAG_NUMFLAGS) - /* Flag does not match anything in the feature tables */ - return -ENOENT; - - feat = &rte_cpu_feature_table[feature]; - - if (!feat->leaf) - /* This entry in the table wasn't filled out! */ - return -EFAULT; - - maxleaf = __get_cpuid_max(feat->leaf & 0x80000000, NULL); - - if (maxleaf < feat->leaf) - return 0; - - __cpuid_count(feat->leaf, feat->subleaf, - regs[RTE_REG_EAX], regs[RTE_REG_EBX], - regs[RTE_REG_ECX], regs[RTE_REG_EDX]); - - /* check if the feature is enabled */ - return (regs[feat->reg] >> feat->bit) & 1; -} - -const char * -rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) -{ - if (feature >= RTE_CPUFLAG_NUMFLAGS) - return NULL; - return rte_cpu_feature_table[feature].name; -} diff --git a/lib/librte_eal/common/arch/x86/rte_cpuid.h b/lib/librte_eal/common/arch/x86/rte_cpuid.h deleted file mode 100644 index b773ad9312..0000000000 --- a/lib/librte_eal/common/arch/x86/rte_cpuid.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2010-2015 Intel Corporation - */ - -#ifndef RTE_CPUID_H -#define RTE_CPUID_H - -#include - -enum cpu_register_t { - RTE_REG_EAX = 0, - RTE_REG_EBX, - RTE_REG_ECX, - RTE_REG_EDX, -}; - -typedef uint32_t cpuid_registers_t[4]; - -#endif /* RTE_CPUID_H */ diff --git a/lib/librte_eal/common/arch/x86/rte_cycles.c b/lib/librte_eal/common/arch/x86/rte_cycles.c deleted file mode 100644 index edd9621abb..0000000000 --- a/lib/librte_eal/common/arch/x86/rte_cycles.c +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017 Intel Corporation - */ - -#include -#include -#include - -#include - -#include "eal_private.h" - -static unsigned int -rte_cpu_get_model(uint32_t fam_mod_step) -{ - uint32_t family, model, ext_model; - - family = (fam_mod_step >> 8) & 0xf; - model = (fam_mod_step >> 4) & 0xf; - - if (family == 6 || family == 15) { - ext_model = (fam_mod_step >> 16) & 0xf; - model += (ext_model << 4); - } - - return model; -} - -static int32_t -rdmsr(int msr, uint64_t *val) -{ -#ifdef RTE_EXEC_ENV_LINUX - int fd; - int ret; - - fd = open("/dev/cpu/0/msr", O_RDONLY); - if (fd < 0) - return fd; - - ret = pread(fd, val, sizeof(uint64_t), msr); - - close(fd); - - return ret; -#else - RTE_SET_USED(msr); - RTE_SET_USED(val); - - return -1; -#endif -} - -static uint32_t -check_model_wsm_nhm(uint8_t model) -{ - switch (model) { - /* Westmere */ - case 0x25: - case 0x2C: - case 0x2F: - /* Nehalem */ - case 0x1E: - case 0x1F: - case 0x1A: - case 0x2E: - return 1; - } - - return 0; -} - -static uint32_t -check_model_gdm_dnv(uint8_t model) -{ - switch (model) { - /* Goldmont */ - case 0x5C: - /* Denverton */ - case 0x5F: - return 1; - } - - return 0; -} - -uint64_t -get_tsc_freq_arch(void) -{ - uint64_t tsc_hz = 0; - uint32_t a, b, c, d, maxleaf; - uint8_t mult, model; - int32_t ret; - - /* - * Time Stamp Counter and Nominal Core Crystal Clock - * Information Leaf - */ - maxleaf = __get_cpuid_max(0, NULL); - - if (maxleaf >= 0x15) { - __cpuid(0x15, a, b, c, d); - - /* EBX : TSC/Crystal ratio, ECX : Crystal Hz */ - if (b && c) - return c * (b / a); - } - - __cpuid(0x1, a, b, c, d); - model = rte_cpu_get_model(a); - - if (check_model_wsm_nhm(model)) - mult = 133; - else if ((c & bit_AVX) || check_model_gdm_dnv(model)) - mult = 100; - else - return 0; - - ret = rdmsr(0xCE, &tsc_hz); - if (ret < 0) - return 0; - - return ((tsc_hz >> 8) & 0xff) * mult * 1E6; -} diff --git a/lib/librte_eal/common/arch/x86/rte_hypervisor.c b/lib/librte_eal/common/arch/x86/rte_hypervisor.c deleted file mode 100644 index c38cfc09df..0000000000 --- a/lib/librte_eal/common/arch/x86/rte_hypervisor.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2017 Mellanox Technologies, Ltd - */ - -#include "rte_hypervisor.h" - -#include -#include - -#include "rte_cpuflags.h" -#include "rte_cpuid.h" - -/* See http://lwn.net/Articles/301888/ */ -#define HYPERVISOR_INFO_LEAF 0x40000000 - -enum rte_hypervisor -rte_hypervisor_get(void) -{ - cpuid_registers_t regs; - int reg; - char name[13]; - - if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_HYPERVISOR)) - return RTE_HYPERVISOR_NONE; - - __cpuid(HYPERVISOR_INFO_LEAF, - regs[RTE_REG_EAX], regs[RTE_REG_EBX], - regs[RTE_REG_ECX], regs[RTE_REG_EDX]); - for (reg = 1; reg < 4; reg++) - memcpy(name + (reg - 1) * 4, ®s[reg], 4); - name[12] = '\0'; - - if (strcmp("KVMKVMKVM", name) == 0) - return RTE_HYPERVISOR_KVM; - if (strcmp("Microsoft Hv", name) == 0) - return RTE_HYPERVISOR_HYPERV; - if (strcmp("VMwareVMware", name) == 0) - return RTE_HYPERVISOR_VMWARE; - return RTE_HYPERVISOR_UNKNOWN; -} diff --git a/lib/librte_eal/common/arch/x86/rte_spinlock.c b/lib/librte_eal/common/arch/x86/rte_spinlock.c deleted file mode 100644 index 34890ea87c..0000000000 --- a/lib/librte_eal/common/arch/x86/rte_spinlock.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2010-2014 Intel Corporation - */ - -#include - -#include "rte_cpuflags.h" - -uint8_t rte_rtm_supported; /* cache the flag to avoid the overhead - of the rte_cpu_get_flag_enabled function */ - -RTE_INIT(rte_rtm_init) -{ - rte_rtm_supported = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RTM); -} diff --git a/lib/librte_eal/common/meson.build b/lib/librte_eal/common/meson.build index 2b97715a20..e666618f7f 100644 --- a/lib/librte_eal/common/meson.build +++ b/lib/librte_eal/common/meson.build @@ -41,13 +41,6 @@ common_sources = files( 'rte_service.c' ) -# get architecture specific sources and objs -eal_common_arch_sources = [] -eal_common_arch_objs = [] -subdir(join_paths('arch', arch_subdir)) -common_sources += eal_common_arch_sources -common_objs += eal_common_arch_objs - common_headers = files( 'include/rte_alarm.h', 'include/rte_branch_prediction.h', diff --git a/lib/librte_eal/freebsd/eal/Makefile b/lib/librte_eal/freebsd/eal/Makefile index b160b57906..e3023f24fa 100644 --- a/lib/librte_eal/freebsd/eal/Makefile +++ b/lib/librte_eal/freebsd/eal/Makefile @@ -7,7 +7,7 @@ LIB = librte_eal.a ARCH_DIR ?= $(RTE_ARCH) VPATH += $(RTE_SDK)/lib/librte_eal/common -VPATH += $(RTE_SDK)/lib/librte_eal/common/arch/$(ARCH_DIR) +VPATH += $(RTE_SDK)/lib/librte_eal/$(ARCH_DIR) CFLAGS += -DALLOW_EXPERIMENTAL_API CFLAGS += -I$(SRCDIR)/include diff --git a/lib/librte_eal/linux/eal/Makefile b/lib/librte_eal/linux/eal/Makefile index e70cf104a4..177b7c45da 100644 --- a/lib/librte_eal/linux/eal/Makefile +++ b/lib/librte_eal/linux/eal/Makefile @@ -8,7 +8,7 @@ LIB = librte_eal.a ARCH_DIR ?= $(RTE_ARCH) EXPORT_MAP := ../../rte_eal_version.map -VPATH += $(RTE_SDK)/lib/librte_eal/common/arch/$(ARCH_DIR) +VPATH += $(RTE_SDK)/lib/librte_eal/$(ARCH_DIR) VPATH += $(RTE_SDK)/lib/librte_eal/common diff --git a/lib/librte_eal/meson.build b/lib/librte_eal/meson.build index 1730d603fc..16a4f9825e 100644 --- a/lib/librte_eal/meson.build +++ b/lib/librte_eal/meson.build @@ -12,6 +12,8 @@ subdir('common') # defines common_sources, common_objs, etc. dpdk_conf.set('RTE_EXEC_ENV_' + exec_env.to_upper(), 1) subdir(exec_env + '/eal') +subdir(arch_subdir) + allow_experimental_apis = true deps += 'kvargs' if dpdk_conf.has('RTE_USE_LIBBSD') @@ -23,7 +25,7 @@ endif if cc.has_header('getopt.h') cflags += ['-DHAVE_GETOPT_H', '-DHAVE_GETOPT', '-DHAVE_GETOPT_LONG'] endif -sources = common_sources + env_sources +sources += common_sources + env_sources objs = common_objs + env_objs headers = common_headers + env_headers includes = eal_inc diff --git a/lib/librte_eal/ppc/meson.build b/lib/librte_eal/ppc/meson.build new file mode 100644 index 0000000000..695b171516 --- /dev/null +++ b/lib/librte_eal/ppc/meson.build @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Luca Boccassi + +sources += files( + 'rte_cpuflags.c', + 'rte_cycles.c', + 'rte_hypervisor.c', +) diff --git a/lib/librte_eal/ppc/rte_cpuflags.c b/lib/librte_eal/ppc/rte_cpuflags.c new file mode 100644 index 0000000000..3bb7563ce9 --- /dev/null +++ b/lib/librte_eal/ppc/rte_cpuflags.c @@ -0,0 +1,110 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) IBM Corporation 2014. + */ + +#include "rte_cpuflags.h" + +#include +#include +#include +#include + +/* Symbolic values for the entries in the auxiliary table */ +#define AT_HWCAP 16 +#define AT_HWCAP2 26 + +/* software based registers */ +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_HWCAP2, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(PPC_LE, REG_HWCAP, 0) + FEAT_DEF(TRUE_LE, REG_HWCAP, 1) + FEAT_DEF(PSERIES_PERFMON_COMPAT, REG_HWCAP, 6) + FEAT_DEF(VSX, REG_HWCAP, 7) + FEAT_DEF(ARCH_2_06, REG_HWCAP, 8) + FEAT_DEF(POWER6_EXT, REG_HWCAP, 9) + FEAT_DEF(DFP, REG_HWCAP, 10) + FEAT_DEF(PA6T, REG_HWCAP, 11) + FEAT_DEF(ARCH_2_05, REG_HWCAP, 12) + FEAT_DEF(ICACHE_SNOOP, REG_HWCAP, 13) + FEAT_DEF(SMT, REG_HWCAP, 14) + FEAT_DEF(BOOKE, REG_HWCAP, 15) + FEAT_DEF(CELLBE, REG_HWCAP, 16) + FEAT_DEF(POWER5_PLUS, REG_HWCAP, 17) + FEAT_DEF(POWER5, REG_HWCAP, 18) + FEAT_DEF(POWER4, REG_HWCAP, 19) + FEAT_DEF(NOTB, REG_HWCAP, 20) + FEAT_DEF(EFP_DOUBLE, REG_HWCAP, 21) + FEAT_DEF(EFP_SINGLE, REG_HWCAP, 22) + FEAT_DEF(SPE, REG_HWCAP, 23) + FEAT_DEF(UNIFIED_CACHE, REG_HWCAP, 24) + FEAT_DEF(4xxMAC, REG_HWCAP, 25) + FEAT_DEF(MMU, REG_HWCAP, 26) + FEAT_DEF(FPU, REG_HWCAP, 27) + FEAT_DEF(ALTIVEC, REG_HWCAP, 28) + FEAT_DEF(PPC601, REG_HWCAP, 29) + FEAT_DEF(PPC64, REG_HWCAP, 30) + FEAT_DEF(PPC32, REG_HWCAP, 31) + FEAT_DEF(TAR, REG_HWCAP2, 26) + FEAT_DEF(LSEL, REG_HWCAP2, 27) + FEAT_DEF(EBB, REG_HWCAP2, 28) + FEAT_DEF(DSCR, REG_HWCAP2, 29) + FEAT_DEF(HTM, REG_HWCAP2, 30) + FEAT_DEF(ARCH_2_07, REG_HWCAP2, 31) +}; + +/* + * Read AUXV software register and get cpu features for Power + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); + out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} diff --git a/lib/librte_eal/ppc/rte_cycles.c b/lib/librte_eal/ppc/rte_cycles.c new file mode 100644 index 0000000000..c96a2143b3 --- /dev/null +++ b/lib/librte_eal/ppc/rte_cycles.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) IBM Corporation 2019. + */ + +#include "eal_private.h" + +uint64_t +get_tsc_freq_arch(void) +{ + return 0; +} diff --git a/lib/librte_eal/ppc/rte_hypervisor.c b/lib/librte_eal/ppc/rte_hypervisor.c new file mode 100644 index 0000000000..08a1c97d10 --- /dev/null +++ b/lib/librte_eal/ppc/rte_hypervisor.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2017 Mellanox Technologies, Ltd + */ + +#include "rte_hypervisor.h" + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + return RTE_HYPERVISOR_UNKNOWN; +} diff --git a/lib/librte_eal/x86/meson.build b/lib/librte_eal/x86/meson.build new file mode 100644 index 0000000000..252699eebd --- /dev/null +++ b/lib/librte_eal/x86/meson.build @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation + +sources += files( + 'rte_cpuflags.c', + 'rte_cycles.c', + 'rte_hypervisor.c', + 'rte_spinlock.c', +) diff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c new file mode 100644 index 0000000000..6492df556c --- /dev/null +++ b/lib/librte_eal/x86/rte_cpuflags.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2015 Intel Corporation + */ + +#include "rte_cpuflags.h" + +#include +#include +#include + +#include "rte_cpuid.h" + +/** + * Struct to hold a processor feature entry + */ +struct feature_entry { + uint32_t leaf; /**< cpuid leaf */ + uint32_t subleaf; /**< cpuid subleaf */ + uint32_t reg; /**< cpuid register */ + uint32_t bit; /**< cpuid register bit */ +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */ +}; + +#define FEAT_DEF(name, leaf, subleaf, reg, bit) \ + [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name }, + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0) + FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1) + FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2) + FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3) + FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4) + FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5) + FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6) + FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7) + FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8) + FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9) + FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10) + FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12) + FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13) + FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14) + FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15) + FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17) + FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18) + FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19) + FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20) + FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21) + FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22) + FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23) + FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24) + FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25) + FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26) + FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27) + FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28) + FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29) + FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30) + FEAT_DEF(HYPERVISOR, 0x00000001, 0, RTE_REG_ECX, 31) + + FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0) + FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1) + FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2) + FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3) + FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4) + FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5) + FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6) + FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7) + FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8) + FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9) + FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11) + FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12) + FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13) + FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14) + FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15) + FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16) + FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17) + FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18) + FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19) + FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21) + FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22) + FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23) + FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24) + FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25) + FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26) + FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27) + FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28) + FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29) + FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31) + + FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0) + FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1) + FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2) + FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4) + FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5) + FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6) + + FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0) + FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1) + FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3) + + FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0) + FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2) + FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4) + FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5) + FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6) + FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7) + FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) + FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) + FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) + FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) + FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18) + + FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) + FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) + + FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11) + FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20) + FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26) + FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27) + FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) + + FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) +}; + +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + cpuid_registers_t regs; + unsigned int maxleaf; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + /* Flag does not match anything in the feature tables */ + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + + if (!feat->leaf) + /* This entry in the table wasn't filled out! */ + return -EFAULT; + + maxleaf = __get_cpuid_max(feat->leaf & 0x80000000, NULL); + + if (maxleaf < feat->leaf) + return 0; + + __cpuid_count(feat->leaf, feat->subleaf, + regs[RTE_REG_EAX], regs[RTE_REG_EBX], + regs[RTE_REG_ECX], regs[RTE_REG_EDX]); + + /* check if the feature is enabled */ + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} diff --git a/lib/librte_eal/x86/rte_cpuid.h b/lib/librte_eal/x86/rte_cpuid.h new file mode 100644 index 0000000000..b773ad9312 --- /dev/null +++ b/lib/librte_eal/x86/rte_cpuid.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2015 Intel Corporation + */ + +#ifndef RTE_CPUID_H +#define RTE_CPUID_H + +#include + +enum cpu_register_t { + RTE_REG_EAX = 0, + RTE_REG_EBX, + RTE_REG_ECX, + RTE_REG_EDX, +}; + +typedef uint32_t cpuid_registers_t[4]; + +#endif /* RTE_CPUID_H */ diff --git a/lib/librte_eal/x86/rte_cycles.c b/lib/librte_eal/x86/rte_cycles.c new file mode 100644 index 0000000000..edd9621abb --- /dev/null +++ b/lib/librte_eal/x86/rte_cycles.c @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Intel Corporation + */ + +#include +#include +#include + +#include + +#include "eal_private.h" + +static unsigned int +rte_cpu_get_model(uint32_t fam_mod_step) +{ + uint32_t family, model, ext_model; + + family = (fam_mod_step >> 8) & 0xf; + model = (fam_mod_step >> 4) & 0xf; + + if (family == 6 || family == 15) { + ext_model = (fam_mod_step >> 16) & 0xf; + model += (ext_model << 4); + } + + return model; +} + +static int32_t +rdmsr(int msr, uint64_t *val) +{ +#ifdef RTE_EXEC_ENV_LINUX + int fd; + int ret; + + fd = open("/dev/cpu/0/msr", O_RDONLY); + if (fd < 0) + return fd; + + ret = pread(fd, val, sizeof(uint64_t), msr); + + close(fd); + + return ret; +#else + RTE_SET_USED(msr); + RTE_SET_USED(val); + + return -1; +#endif +} + +static uint32_t +check_model_wsm_nhm(uint8_t model) +{ + switch (model) { + /* Westmere */ + case 0x25: + case 0x2C: + case 0x2F: + /* Nehalem */ + case 0x1E: + case 0x1F: + case 0x1A: + case 0x2E: + return 1; + } + + return 0; +} + +static uint32_t +check_model_gdm_dnv(uint8_t model) +{ + switch (model) { + /* Goldmont */ + case 0x5C: + /* Denverton */ + case 0x5F: + return 1; + } + + return 0; +} + +uint64_t +get_tsc_freq_arch(void) +{ + uint64_t tsc_hz = 0; + uint32_t a, b, c, d, maxleaf; + uint8_t mult, model; + int32_t ret; + + /* + * Time Stamp Counter and Nominal Core Crystal Clock + * Information Leaf + */ + maxleaf = __get_cpuid_max(0, NULL); + + if (maxleaf >= 0x15) { + __cpuid(0x15, a, b, c, d); + + /* EBX : TSC/Crystal ratio, ECX : Crystal Hz */ + if (b && c) + return c * (b / a); + } + + __cpuid(0x1, a, b, c, d); + model = rte_cpu_get_model(a); + + if (check_model_wsm_nhm(model)) + mult = 133; + else if ((c & bit_AVX) || check_model_gdm_dnv(model)) + mult = 100; + else + return 0; + + ret = rdmsr(0xCE, &tsc_hz); + if (ret < 0) + return 0; + + return ((tsc_hz >> 8) & 0xff) * mult * 1E6; +} diff --git a/lib/librte_eal/x86/rte_hypervisor.c b/lib/librte_eal/x86/rte_hypervisor.c new file mode 100644 index 0000000000..c38cfc09df --- /dev/null +++ b/lib/librte_eal/x86/rte_hypervisor.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2017 Mellanox Technologies, Ltd + */ + +#include "rte_hypervisor.h" + +#include +#include + +#include "rte_cpuflags.h" +#include "rte_cpuid.h" + +/* See http://lwn.net/Articles/301888/ */ +#define HYPERVISOR_INFO_LEAF 0x40000000 + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + cpuid_registers_t regs; + int reg; + char name[13]; + + if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_HYPERVISOR)) + return RTE_HYPERVISOR_NONE; + + __cpuid(HYPERVISOR_INFO_LEAF, + regs[RTE_REG_EAX], regs[RTE_REG_EBX], + regs[RTE_REG_ECX], regs[RTE_REG_EDX]); + for (reg = 1; reg < 4; reg++) + memcpy(name + (reg - 1) * 4, ®s[reg], 4); + name[12] = '\0'; + + if (strcmp("KVMKVMKVM", name) == 0) + return RTE_HYPERVISOR_KVM; + if (strcmp("Microsoft Hv", name) == 0) + return RTE_HYPERVISOR_HYPERV; + if (strcmp("VMwareVMware", name) == 0) + return RTE_HYPERVISOR_VMWARE; + return RTE_HYPERVISOR_UNKNOWN; +} diff --git a/lib/librte_eal/x86/rte_spinlock.c b/lib/librte_eal/x86/rte_spinlock.c new file mode 100644 index 0000000000..34890ea87c --- /dev/null +++ b/lib/librte_eal/x86/rte_spinlock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2014 Intel Corporation + */ + +#include + +#include "rte_cpuflags.h" + +uint8_t rte_rtm_supported; /* cache the flag to avoid the overhead + of the rte_cpu_get_flag_enabled function */ + +RTE_INIT(rte_rtm_init) +{ + rte_rtm_supported = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RTM); +}