From: Lance Richardson <lance.richardson@broadcom.com>
Date: Sun, 2 Jun 2019 17:42:36 +0000 (-0400)
Subject: net/bnxt: fix endianness in ring macros
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=3858965c3a266c2d9350402cf4f2f420de686a62;p=dpdk.git

net/bnxt: fix endianness in ring macros

Descriptor fields in CP ring are in little-endian form, convert
to CPU endian before performing arithmetic operations.

Also use more general comparison when checking for ring
index wrap.

Fixes: f2a768d4d186 ("net/bnxt: add completion ring")
Cc: stable@dpdk.org

Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---

diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index c7af569833..ee5ca820e6 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -10,11 +10,12 @@
 #include <rte_io.h>
 
 #define CMP_VALID(cmp, raw_cons, ring)					\
-	(!!(((struct cmpl_base *)(cmp))->info3_v & CMPL_BASE_V) ==	\
-	 !((raw_cons) & ((ring)->ring_size)))
+	(!!(rte_le_to_cpu_32(((struct cmpl_base *)(cmp))->info3_v) &	\
+	    CMPL_BASE_V) == !((raw_cons) & ((ring)->ring_size)))
 
 #define CMPL_VALID(cmp, v)						\
-	(!!(((struct cmpl_base *)(cmp))->info3_v & CMPL_BASE_V) == !(v))
+	(!!(rte_le_to_cpu_32(((struct cmpl_base *)(cmp))->info3_v) &	\
+	    CMPL_BASE_V) == !(v))
 
 #define CMP_TYPE(cmp)						\
 	(((struct cmpl_base *)cmp)->type & CMPL_BASE_TYPE_MASK)
@@ -31,7 +32,7 @@
 
 #define NEXT_CMPL(cpr, idx, v, inc)	do { \
 	(idx) += (inc); \
-	if (unlikely((idx) == (cpr)->cp_ring_struct->ring_size)) { \
+	if (unlikely((idx) >= (cpr)->cp_ring_struct->ring_size)) { \
 		(v) = !(v); \
 		(idx) = 0; \
 	} \