From: Viacheslav Ovsiienko Date: Fri, 17 Jan 2020 14:59:32 +0000 (+0000) Subject: net/mlx5: fix metadata item endianness conversion X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=39c09c22e5b5c46cf8f44826a1c759e036f3af3a;p=dpdk.git net/mlx5: fix metadata item endianness conversion The mlx5 datapath does not implement any endianness conversions for the metadata being sent and received to provide the better performance (because these conversions would be performed for each packet). These metadata are also involved into flow processing (there might be some flows matching on metadata patterns or setting the new metadata values) inside the NIC. It order to configure hardware in correct way all necessary endianness conversions are done by rte_flow handling code (only once on flow creation). This patch fixes one of these conversions for the little-endian hosts in case if META/MARK items are less than 32 bits. Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index da988f9dd7..c02517aaf3 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6081,8 +6081,12 @@ flow_dv_translate_item_meta(struct rte_eth_dev *dev, struct mlx5_priv *priv = dev->data->dev_private; uint32_t msk_c0 = priv->sh->dv_regc0_mask; uint32_t shl_c0 = rte_bsf32(msk_c0); +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask); - msk_c0 = rte_cpu_to_be_32(msk_c0); + value >>= shr_c0; + mask >>= shr_c0; +#endif value <<= shl_c0; mask <<= shl_c0; assert(msk_c0);