From: Pavan Nikhilesh Date: Mon, 13 Dec 2021 11:06:14 +0000 (+0530) Subject: config: align mempool elements to 128 bytes on CN10K X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=3e97fa671dee32ea2689eb18f868d9086613cc1b;p=dpdk.git config: align mempool elements to 128 bytes on CN10K Mempool elements are by default aligned to CACHELINE_SIZE. In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to 128B. Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned 128 bytes. Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh Reviewed-by: Ruifeng Wang --- diff --git a/config/arm/meson.build b/config/arm/meson.build index dd5e2f38d4..48b88a84f2 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -277,7 +277,8 @@ soc_cn10k = { 'implementer' : '0x41', 'flags': [ ['RTE_MAX_LCORE', 24], - ['RTE_MAX_NUMA_NODES', 1] + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MEMPOOL_ALIGN', 128] ], 'part_number': '0xd49', 'extra_march_features': ['crypto'],