From: Pavan Nikhilesh Date: Fri, 28 Jun 2019 18:23:12 +0000 (+0530) Subject: event/octeontx2: add build infra and device probe X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=3ef6bbfeadb89191dda296c07afb35c7c971dd07;p=dpdk.git event/octeontx2: add build infra and device probe Add the make and meson based build infrastructure along with the eventdev(SSO) device probe. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh Signed-off-by: Nithin Dabilpuram --- diff --git a/MAINTAINERS b/MAINTAINERS index b3d43d83f0..9eb96eb2d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1044,6 +1044,12 @@ Cavium OCTEON TX timvf M: Pavan Nikhilesh F: drivers/event/octeontx/timvf_* +Marvell OCTEON TX2 +M: Pavan Nikhilesh +M: Jerin Jacob +F: drivers/event/octeontx2/ +F: doc/guides/eventdevs/octeontx2.rst + NXP DPAA eventdev M: Hemant Agrawal M: Sunil Kumar Kori diff --git a/config/common_base b/config/common_base index e700bf1e78..5318868a72 100644 --- a/config/common_base +++ b/config/common_base @@ -714,6 +714,11 @@ CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV=y # CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF=y +# +# Compile PMD for octeontx2 sso event device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV=y + # # Compile PMD for OPDL event device # diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst index f7382dc8a3..570905b813 100644 --- a/doc/guides/eventdevs/index.rst +++ b/doc/guides/eventdevs/index.rst @@ -16,4 +16,5 @@ application trough the eventdev API. dsw sw octeontx + octeontx2 opdl diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst new file mode 100644 index 0000000000..341c5b21dd --- /dev/null +++ b/doc/guides/eventdevs/octeontx2.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2019 Marvell International Ltd. + +OCTEON TX2 SSO Eventdev Driver +=============================== + +The OCTEON TX2 SSO PMD (**librte_pmd_octeontx2_event**) provides poll mode +eventdev driver support for the inbuilt event device found in the **Marvell OCTEON TX2** +SoC family. + +More information about OCTEON TX2 SoC can be found at `Marvell Official Website +`_. + +Features +-------- + +Features of the OCTEON TX2 SSO PMD are: + +- 256 Event queues +- 26 (dual) and 52 (single) Event ports +- HW event scheduler +- Supports 1M flows per event queue +- Flow based event pipelining +- Flow pinning support in flow based event pipelining +- Queue based event pipelining +- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow +- Event scheduling QoS based on event queue priority +- Open system with configurable amount of outstanding events limited only by + DRAM +- HW accelerated dequeue timeout support to enable power management + +Prerequisites and Compilation procedure +--------------------------------------- + + See :doc:`../platform/octeontx2` for setup information. + +Pre-Installation Configuration +------------------------------ + +Compile time Config Options +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following option can be modified in the ``config`` file. + +- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV`` (default ``y``) + + Toggle compilation of the ``librte_pmd_octeontx2_event`` driver. + +Debugging Options +~~~~~~~~~~~~~~~~~ + +.. _table_octeontx2_event_debug_options: + +.. table:: OCTEON TX2 event device debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | SSO | --log-level='pmd\.event\.octeontx2,8' | + +---+------------+-------------------------------------------------------+ diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst index c9ea456478..fbf1193e74 100644 --- a/doc/guides/platform/octeontx2.rst +++ b/doc/guides/platform/octeontx2.rst @@ -101,6 +101,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC. #. **Mempool Driver** See :doc:`../mempool/octeontx2` for NPA mempool driver information. +#. **Event Device Driver** + See :doc:`../eventdevs/octeontx2` for SSO event device driver information. + Procedure to Setup Platform --------------------------- diff --git a/drivers/event/Makefile b/drivers/event/Makefile index 03ad1b6cb8..86be41b9eb 100644 --- a/drivers/event/Makefile +++ b/drivers/event/Makefile @@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV) += skeleton DIRS-$(CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV) += sw DIRS-$(CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV) += dsw DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += octeontx +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += octeontx2 ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y) DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV) += dpaa endif diff --git a/drivers/event/meson.build b/drivers/event/meson.build index fb723f727b..50d30c53fc 100644 --- a/drivers/event/meson.build +++ b/drivers/event/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['dpaa', 'dpaa2', 'opdl', 'skeleton', 'sw', 'dsw'] +drivers = ['dpaa', 'dpaa2', 'octeontx2', 'opdl', 'skeleton', 'sw', 'dsw'] if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and dpdk_conf.has('RTE_ARCH_ARM64')) drivers += 'octeontx' diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile new file mode 100644 index 0000000000..a81da72962 --- /dev/null +++ b/drivers/event/octeontx2/Makefile @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. +# + +include $(RTE_SDK)/mk/rte.vars.mk + +# +# library name +# +LIB = librte_pmd_octeontx2_event.a + +CFLAGS += $(WERROR_FLAGS) +CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2 +CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2 +CFLAGS += -I$(RTE_SDK)/drivers/event/octeontx2 +CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2 +CFLAGS += -O3 +CFLAGS += -DALLOW_EXPERIMENTAL_API + +ifneq ($(CONFIG_RTE_ARCH_64),y) +CFLAGS += -Wno-int-to-pointer-cast +CFLAGS += -Wno-pointer-to-int-cast +ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y) +CFLAGS += -diag-disable 2259 +endif +endif + +EXPORT_MAP := rte_pmd_octeontx2_event_version.map + +LIBABIVER := 1 + +# +# all source are stored in SRCS-y +# + +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c + +LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci +LDLIBS += -lrte_eventdev +LDLIBS += -lrte_common_octeontx2 + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build new file mode 100644 index 0000000000..c4f4421749 --- /dev/null +++ b/drivers/event/octeontx2/meson.build @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. +# + +sources = files('otx2_evdev.c') + +allow_experimental_apis = true + +extra_flags = [] +# This integrated controller runs only on a arm64 machine, remove 32bit warnings +if not dpdk_conf.get('RTE_ARCH_64') + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast'] +endif + +foreach flag: extra_flags + if cc.has_argument(flag) + cflags += flag + endif +endforeach + +deps += ['bus_pci', 'common_octeontx2'] diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c new file mode 100644 index 0000000000..faffd3f0c6 --- /dev/null +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include + +#include +#include +#include +#include +#include + +#include "otx2_evdev.h" + +static int +otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_probe(pci_drv, pci_dev, + sizeof(struct otx2_sso_evdev), + otx2_sso_init); +} + +static int +otx2_sso_remove(struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini); +} + +static const struct rte_pci_id pci_sso_map[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF) + }, + { + .vendor_id = 0, + }, +}; + +static struct rte_pci_driver pci_sso = { + .id_table = pci_sso_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, + .probe = otx2_sso_probe, + .remove = otx2_sso_remove, +}; + +int +otx2_sso_init(struct rte_eventdev *event_dev) +{ + RTE_SET_USED(event_dev); + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + return 0; +} + +int +otx2_sso_fini(struct rte_eventdev *event_dev) +{ + RTE_SET_USED(event_dev); + /* For secondary processes, nothing to be done */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + return 0; +} + +RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso); +RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map); +RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci"); diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h new file mode 100644 index 0000000000..1df2332930 --- /dev/null +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef __OTX2_EVDEV_H__ +#define __OTX2_EVDEV_H__ + +#include + +#include "otx2_common.h" + +#define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev + +#define sso_func_trace otx2_sso_dbg + +#define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV +#define OTX2_SSO_MAX_VHWS (UINT8_MAX) + +struct otx2_sso_evdev { +}; + +/* Init and Fini API's */ +int otx2_sso_init(struct rte_eventdev *event_dev); +int otx2_sso_fini(struct rte_eventdev *event_dev); + +#endif /* __OTX2_EVDEV_H__ */ diff --git a/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map b/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map new file mode 100644 index 0000000000..41c65c8c9c --- /dev/null +++ b/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map @@ -0,0 +1,4 @@ +DPDK_19.08 { + local: *; +}; + diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 2b5696a27e..55ffba46eb 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -109,6 +109,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO _LDLIBS-y += -lrte_common_octeontx endif OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) +OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) ifeq ($(findstring y,$(OCTEONTX2-y)),y) _LDLIBS-y += -lrte_common_octeontx2 endif @@ -293,6 +294,7 @@ endif # CONFIG_RTE_LIBRTE_FSLMC_BUS _LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += -lrte_mempool_octeontx _LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX_PMD) += -lrte_pmd_octeontx +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += -lrte_pmd_octeontx2_event _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPDL_EVENTDEV) += -lrte_pmd_opdl_event endif # CONFIG_RTE_LIBRTE_EVENTDEV