From: Tianfei Zhang <tianfei.zhang@intel.com>
Date: Thu, 14 Nov 2019 09:03:03 +0000 (+0800)
Subject: raw/ifpga/base: clean FME errors
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=4858f8a588fb800e547eb4f30dedb5772a40b1ec;p=dpdk.git

raw/ifpga/base: clean FME errors

Clean fme errors register when some fme errors occurred.

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
---

diff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c b/drivers/raw/ifpga/base/ifpga_fme_error.c
index 5d6d630505..5905eac260 100644
--- a/drivers/raw/ifpga/base/ifpga_fme_error.c
+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c
@@ -48,34 +48,14 @@ static int fme_err_set_clear(struct ifpga_fme_hw *fme, u64 val)
 	struct feature_fme_err *fme_err
 		= get_fme_feature_ioaddr_by_index(fme,
 						  FME_FEATURE_ID_GLOBAL_ERR);
-	struct feature_fme_error0 fme_error0;
-	struct feature_fme_first_error fme_first_err;
-	struct feature_fme_next_error fme_next_err;
-	int ret = 0;
 
 	spinlock_lock(&fme->lock);
-	writeq(GENMASK_ULL(63, 0), &fme_err->fme_err_mask);
-
-	fme_error0.csr = readq(&fme_err->fme_err);
-	if (val != fme_error0.csr) {
-		ret = -EBUSY;
-		goto exit;
-	}
-
-	fme_first_err.csr = readq(&fme_err->fme_first_err);
-	fme_next_err.csr = readq(&fme_err->fme_next_err);
 
-	writeq(fme_error0.csr, &fme_err->fme_err);
-	writeq(fme_first_err.csr & FME_FIRST_ERROR_MASK,
-	       &fme_err->fme_first_err);
-	writeq(fme_next_err.csr & FME_NEXT_ERROR_MASK,
-	       &fme_err->fme_next_err);
+	writeq(val, &fme_err->fme_err);
 
-exit:
-	writeq(FME_ERROR0_MASK_DEFAULT, &fme_err->fme_err_mask);
 	spinlock_unlock(&fme->lock);
 
-	return ret;
+	return 0;
 }
 
 static int fme_err_get_revision(struct ifpga_fme_hw *fme, u64 *val)
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
index 85d91c0f12..73f0f8ce2b 100644
--- a/drivers/raw/ifpga/ifpga_rawdev.c
+++ b/drivers/raw/ifpga/ifpga_rawdev.c
@@ -1175,6 +1175,25 @@ static int fme_clear_warning_intr(struct opae_manager *mgr)
 	return 0;
 }
 
+static int fme_clean_fme_error(struct opae_manager *mgr)
+{
+	u64 val;
+
+	if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
+		return -EINVAL;
+
+	IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
+
+	ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
+
+	if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
+		return -EINVAL;
+
+	IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
+
+	return 0;
+}
+
 static int
 fme_err_handle_error0(struct opae_manager *mgr)
 {
@@ -1184,6 +1203,9 @@ fme_err_handle_error0(struct opae_manager *mgr)
 	if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
 		return -EINVAL;
 
+	if (fme_clean_fme_error(mgr))
+		return -EINVAL;
+
 	fme_error0.csr = val;
 
 	if (fme_error0.fabric_err)