From: Jerin Jacob Date: Fri, 26 Jul 2019 05:24:43 +0000 (+0530) Subject: common/octeontx2: prevent STP instruction fissure X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=5077d8887930e435b6c2120fa717f9fafa2d963d;p=dpdk.git common/octeontx2: prevent STP instruction fissure OTX2 AP core can sometimes fissure STP instructions when it is more optimal to send such writes into the pipeline as 2 separate instructions. However registers should be excluded from such optimization. This commit ensures that no CSR write is ever fissured by introducing zero cost workaround by setting STP pre-index by zero to make sure OTX2 AP core prevent fissure. Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") Signed-off-by: Jerin Jacob Acked-by: Pavan Nikhilesh --- diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h index 468243c042..7e45329b38 100644 --- a/drivers/common/octeontx2/otx2_io_arm64.h +++ b/drivers/common/octeontx2/otx2_io_arm64.h @@ -14,7 +14,7 @@ #define otx2_store_pair(val0, val1, addr) ({ \ asm volatile( \ - "stp %x[x0], %x[x1], [%x[p1]]" \ + "stp %x[x0], %x[x1], [%x[p1],#0]!" \ ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \ ); })