From: Chao Zhu Date: Tue, 25 Nov 2014 22:17:13 +0000 (-0500) Subject: mk: define cache size for IBM Power X-Git-Tag: spdx-start~10046 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=536681d7e9e8866c97a4c768aa24af0dca377e5f;p=dpdk.git mk: define cache size for IBM Power IBM Power architecture has different cache line size (128 bytes) than x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to override the default value 64 bytes to support IBM Power Architecture. Signed-off-by: Chao Zhu Acked-by: David Marchand --- diff --git a/app/test/test_malloc.c b/app/test/test_malloc.c index ee34ca3bed..63e6b32d25 100644 --- a/app/test/test_malloc.c +++ b/app/test/test_malloc.c @@ -300,9 +300,9 @@ test_big_alloc(void) size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2; int align = 0; #ifndef RTE_LIBRTE_MALLOC_DEBUG - int overhead = 64 + 64; + int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE; #else - int overhead = 64 + 64 + 64; + int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE; #endif rte_malloc_get_socket_stats(socket, &pre_stats); @@ -356,9 +356,9 @@ test_multi_alloc_statistics(void) #ifndef RTE_LIBRTE_MALLOC_DEBUG int trailer_size = 0; #else - int trailer_size = 64; + int trailer_size = CACHE_LINE_SIZE; #endif - int overhead = 64 + trailer_size; + int overhead = CACHE_LINE_SIZE + trailer_size; rte_malloc_get_socket_stats(socket, &pre_stats); diff --git a/mk/arch/ppc_64/rte.vars.mk b/mk/arch/ppc_64/rte.vars.mk index 363fcd14b9..dfdeaeafc3 100644 --- a/mk/arch/ppc_64/rte.vars.mk +++ b/mk/arch/ppc_64/rte.vars.mk @@ -32,7 +32,7 @@ ARCH ?= powerpc CROSS ?= -CPU_CFLAGS ?= -m64 +CPU_CFLAGS ?= -m64 -DCACHE_LINE_SIZE=128 CPU_LDFLAGS ?= CPU_ASFLAGS ?= -felf64