From: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Date: Fri, 6 May 2016 07:43:16 +0000 (+0530)
Subject: net/cxgbe: access to PCI config space
X-Git-Tag: spdx-start~6563
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=5c81b1a9e885d54acd238274de2075b43a72882a;p=dpdk.git

net/cxgbe: access to PCI config space

Add helper functions to read/write PCI config space.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
---

diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h
index a5225c0e91..af34721454 100644
--- a/drivers/net/cxgbe/base/adapter.h
+++ b/drivers/net/cxgbe/base/adapter.h
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2014-2015 Chelsio Communications.
+ *   Copyright(c) 2014-2016 Chelsio Communications.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -427,6 +427,133 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
 	CXGBE_WRITE_REG64(adapter, reg_addr, val);
 }
 
+#define PCI_STATUS              0x06    /* 16 bits */
+#define PCI_STATUS_CAP_LIST     0x10    /* Support Capability List */
+#define PCI_CAPABILITY_LIST     0x34
+/* Offset of first capability list entry */
+#define PCI_CAP_LIST_ID         0       /* Capability ID */
+#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
+
+/**
+ * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
+ * @adapter: the adapter
+ * @addr: the register address
+ * @val: the value to write
+ *
+ * Write a 32-bit value into the given register in PCI config space.
+ */
+static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
+					off_t val)
+{
+	u32 val32 = val;
+
+	if (rte_eal_pci_write_config(adapter->pdev, &val32, sizeof(val32),
+				     addr) < 0)
+		dev_err(adapter, "Can't write to PCI config space\n");
+}
+
+/**
+ * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
+ * @adapter: the adapter
+ * @addr: the register address
+ * @val: where to store the value read
+ *
+ * Read a 32-bit value from the given register in PCI config space.
+ */
+static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
+				       u32 *val)
+{
+	if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val),
+				    addr) < 0)
+		dev_err(adapter, "Can't read from PCI config space\n");
+}
+
+/**
+ * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
+ * @adapter: the adapter
+ * @addr: the register address
+ * @val: the value to write
+ *
+ * Write a 16-bit value into the given register in PCI config space.
+ */
+static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
+					off_t val)
+{
+	u16 val16 = val;
+
+	if (rte_eal_pci_write_config(adapter->pdev, &val16, sizeof(val16),
+				     addr) < 0)
+		dev_err(adapter, "Can't write to PCI config space\n");
+}
+
+/**
+ * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
+ * @adapter: the adapter
+ * @addr: the register address
+ * @val: where to store the value read
+ *
+ * Read a 16-bit value from the given register in PCI config space.
+ */
+static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
+				       u16 *val)
+{
+	if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val),
+				    addr) < 0)
+		dev_err(adapter, "Can't read from PCI config space\n");
+}
+
+/**
+ * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
+ * @adapter: the adapter
+ * @addr: the register address
+ * @val: where to store the value read
+ *
+ * Read a 8-bit value from the given register in PCI config space.
+ */
+static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
+				      u8 *val)
+{
+	if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val),
+				    addr) < 0)
+		dev_err(adapter, "Can't read from PCI config space\n");
+}
+
+/**
+ * t4_os_find_pci_capability - lookup a capability in the PCI capability list
+ * @adapter: the adapter
+ * @cap: the capability
+ *
+ * Return the address of the given capability within the PCI capability list.
+ */
+static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
+{
+	u16 status;
+	int ttl = 48;
+	u8 pos = 0;
+	u8 id = 0;
+
+	t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status);
+	if (!(status & PCI_STATUS_CAP_LIST)) {
+		dev_err(adapter, "PCIe capability reading failed\n");
+		return -1;
+	}
+
+	t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos);
+	while (ttl-- && pos >= 0x40) {
+		pos &= ~3;
+		t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id);
+
+		if (id == 0xff)
+			break;
+
+		if (id == cap)
+			return (int)pos;
+
+		t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos);
+	}
+	return 0;
+}
+
 /**
  * t4_os_set_hw_addr - store a port's MAC address in SW
  * @adapter: the adapter