From: Beilei Xing <beilei.xing@intel.com>
Date: Thu, 23 Jun 2016 07:22:33 +0000 (+0800)
Subject: net/ixgbe/base: fix endianness
X-Git-Tag: spdx-start~6359
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=7887b024640239fa051b63825539643f16128aac;p=dpdk.git

net/ixgbe/base: fix endianness

This patch fixes endianness issues about host interface command.

Fixes: ad66a85dce9a ("ixgbe/base: new FW values")
Fixes: 0790adeb5675 ("ixgbe/base: support X550em_a device")

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---

diff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h
index 40b0b51240..31cc1bef8b 100644
--- a/drivers/net/ixgbe/base/ixgbe_osdep.h
+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h
@@ -96,6 +96,7 @@ enum {
 #define IXGBE_NTOHL(_i)	rte_be_to_cpu_32(_i)
 #define IXGBE_NTOHS(_i)	rte_be_to_cpu_16(_i)
 #define IXGBE_CPU_TO_LE32(_i)  rte_cpu_to_le_32(_i)
+#define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)
 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
 #define IXGBE_CPU_TO_BE16(_i)  rte_cpu_to_be_16(_i)
 #define IXGBE_CPU_TO_BE32(_i)  rte_cpu_to_be_32(_i)
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index d91c4ed2f2..5d76c72a5e 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -3050,6 +3050,12 @@ enum ixgbe_fdir_pballoc_type {
 
 /* Host Interface Command Structures */
 
+#ifdef C99
+#pragma pack(push, 1)
+#else
+#pragma pack(1)
+#endif /* C99 */
+
 struct ixgbe_hic_hdr {
 	u8 cmd;
 	u8 buf_len;
@@ -3127,17 +3133,22 @@ struct ixgbe_hic_internal_phy_req {
 	struct ixgbe_hic_hdr hdr;
 	u8 port_number;
 	u8 command_type;
-	u16 address;
+	__be16 address;
 	u16 rsv1;
-	u32 write_data;
+	__le32 write_data;
 	u16 pad;
 };
 
 struct ixgbe_hic_internal_phy_resp {
 	struct ixgbe_hic_hdr hdr;
-	u32 read_data;
+	__le32 read_data;
 };
 
+#ifdef C99
+#pragma pack(pop)
+#else
+#pragma pack()
+#endif /* C99 */
 
 /* Transmit Descriptor - Legacy */
 struct ixgbe_legacy_tx_desc {
diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c
index 06b791b942..dfa28559c3 100644
--- a/drivers/net/ixgbe/base/ixgbe_x550.c
+++ b/drivers/net/ixgbe/base/ixgbe_x550.c
@@ -1273,8 +1273,8 @@ s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 	write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 	write_cmd.port_number = hw->bus.lan_id;
 	write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
-	write_cmd.address = (u16)reg_addr;
-	write_cmd.write_data = data;
+	write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
+	write_cmd.write_data = IXGBE_CPU_TO_LE32(data);
 
 	status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
 					      sizeof(write_cmd),
@@ -1294,24 +1294,27 @@ s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 				 u32 device_type, u32 *data)
 {
-	struct ixgbe_hic_internal_phy_req read_cmd;
+	union {
+		struct ixgbe_hic_internal_phy_req cmd;
+		struct ixgbe_hic_internal_phy_resp rsp;
+	} hic;
 	s32 status;
 	UNREFERENCED_1PARAMETER(device_type);
 
-	memset(&read_cmd, 0, sizeof(read_cmd));
-	read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
-	read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
-	read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
-	read_cmd.port_number = hw->bus.lan_id;
-	read_cmd.command_type = FW_INT_PHY_REQ_READ;
-	read_cmd.address = (u16)reg_addr;
+	memset(&hic, 0, sizeof(hic));
+	hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
+	hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
+	hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
+	hic.cmd.port_number = hw->bus.lan_id;
+	hic.cmd.command_type = FW_INT_PHY_REQ_READ;
+	hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
 
-	status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
-					      sizeof(read_cmd),
+	status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
+					      sizeof(hic.cmd),
 					      IXGBE_HI_COMMAND_TIMEOUT, true);
 
 	/* Extract the register value from the response. */
-	*data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
+	*data = IXGBE_LE32_TO_CPU(hic.rsp.read_data);
 
 	return status;
 }