From: Shahed Shaikh <shahed.shaikh@cavium.com>
Date: Sat, 8 Sep 2018 20:31:05 +0000 (-0700)
Subject: net/qede/base: fix MFW FLR flow
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=797ce8eec7c1b9e37dd9398403e9bc888cca0013;p=dpdk.git

net/qede/base: fix MFW FLR flow

Management firmware does not properly clean IGU block in PF FLR flow
which may result in undelivered attentions for link events from
default status block.
Add a workaround in PMD to execute extra IGU cleanup right after PF FLR
is done.

Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before load request")
Cc: stable@dpdk.org

Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
---

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index fdb62f2329..d91fe27471 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -4272,6 +4272,13 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
 		rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
 		if (rc != ECORE_SUCCESS)
 			DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
+
+		/* Workaround for MFW issue where PF FLR does not cleanup
+		 * IGU block
+		 */
+		if (!(p_hwfn->mcp_info->capabilities &
+		      FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
+			ecore_pf_flr_igu_cleanup(p_hwfn);
 	}
 
 	/* Check if mdump logs/data are present and update the epoch value */
diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c
index 4c271d3581..d41107d49b 100644
--- a/drivers/net/qede/base/ecore_int.c
+++ b/drivers/net/qede/base/ecore_int.c
@@ -2681,3 +2681,35 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
 
 	return ECORE_SUCCESS;
 }
+
+void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn)
+{
+	struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
+	struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
+							     RESERVED_PTT_DPC);
+	int i;
+
+	/* Do not reorder the following cleanup sequence */
+	/* Ack all attentions */
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
+
+	/* Clear driver attention */
+	ecore_wr(p_hwfn,  p_dpc_ptt,
+		((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0);
+
+	/* Clear per-PF IGU registers to restore them as if the IGU
+	 * was reset for this PF
+	 */
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
+
+	/* Execute IGU clean up*/
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
+
+	/* Clear Stats */
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0);
+
+	for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
+		ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
+}
diff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h
index 041240d7b9..ff2310cff4 100644
--- a/drivers/net/qede/base/ecore_int.h
+++ b/drivers/net/qede/base/ecore_int.h
@@ -256,5 +256,6 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 						   struct ecore_ptt *p_ptt,
 						   bool is_hw_init);
+void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn);
 
 #endif /* __ECORE_INT_H__ */
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index e9f335096f..2ee8ab538c 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -1797,6 +1797,8 @@ struct public_drv_mb {
 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
 /* MFW supports DRV_LOAD Timeout */
 #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO  0x00000004
+/* MFW support complete IGU cleanup upon FLR */
+#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP	0x00000080
 /* MFW supports virtual link */
 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK       0x00010000
 
diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h
index 7ed26fcced..b82ccc1cdd 100644
--- a/drivers/net/qede/base/reg_addr.h
+++ b/drivers/net/qede/base/reg_addr.h
@@ -322,6 +322,21 @@
 	0x180820UL
 #define  IGU_REG_ATTN_MSG_ADDR_H	\
 	0x180824UL
+#define IGU_REG_LEADING_EDGE_LATCH \
+	0x18082cUL
+#define IGU_REG_TRAILING_EDGE_LATCH \
+	0x180830UL
+#define IGU_REG_ATTENTION_ACK_BITS \
+	0x180838UL
+#define IGU_REG_PBA_STS_PF \
+	0x180d20UL
+#define IGU_REG_PF_FUNCTIONAL_CLEANUP \
+	0x181210UL
+#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \
+	0x18042cUL
+#define IGU_REG_PBA_STS_PF_SIZE 5
+#define IGU_REG_PBA_STS_PF \
+	0x180d20UL
 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
 	0x008400UL
 #define  CAU_REG_SB_ADDR_MEMORY \