From: Intel Date: Wed, 19 Dec 2012 23:00:00 +0000 (+0100) Subject: e1000: minor changes in base driver X-Git-Tag: spdx-start~11361 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=7ea63c1f744ee50825fdfe6b6284224c29639f1a;p=dpdk.git e1000: minor changes in base driver Signed-off-by: Intel --- diff --git a/lib/librte_pmd_e1000/e1000/e1000_82575.c b/lib/librte_pmd_e1000/e1000/e1000_82575.c index b10a415a64..60e870db2f 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_82575.c +++ b/lib/librte_pmd_e1000/e1000/e1000_82575.c @@ -41,60 +41,60 @@ POSSIBILITY OF SUCH DAMAGE. #include "e1000_api.h" -static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); -static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); -static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); -static void e1000_release_phy_82575(struct e1000_hw *hw); -static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); -static void e1000_release_nvm_82575(struct e1000_hw *hw); -static s32 e1000_check_for_link_82575(struct e1000_hw *hw); -static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); -static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, +STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw); +STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw); +STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw); +STATIC void e1000_release_phy_82575(struct e1000_hw *hw); +STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); +STATIC void e1000_release_nvm_82575(struct e1000_hw *hw); +STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw); +STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); +STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex); -static s32 e1000_init_hw_82575(struct e1000_hw *hw); -static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); -static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, +STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw); +STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); +STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data); -static s32 e1000_reset_hw_82575(struct e1000_hw *hw); -static s32 e1000_reset_hw_82580(struct e1000_hw *hw); -static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, +STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw); +STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw); +STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data); -static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, +STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data); -static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, +STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active); -static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, +STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active); -static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, +STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active); -static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); -static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); -static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); -static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, +STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); +STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); +STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); +STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data); -static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); -static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); +STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); +STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex); static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); -static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); +STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); static bool e1000_sgmii_active_82575(struct e1000_hw *hw); -static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); -static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); -static void e1000_config_collision_dist_82575(struct e1000_hw *hw); -static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); -static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); -static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); -static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); -static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); -static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); -static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); -static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, +STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw); +STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); +STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw); +STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); +STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); +STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); +STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); +STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); +STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); +STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); +STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset); -static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, +STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset); -static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); -static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); +STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); +STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); static const u16 e1000_82580_rxpbs_table[] = { 36, 72, 144, 1, 2, 4, 8, 16, @@ -110,10 +110,10 @@ static const u16 e1000_82580_rxpbs_table[] = * Called to determine if the I2C pins are being used for I2C or as an * external MDIO interface since the two options are mutually exclusive. **/ -static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) +STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) { u32 reg = 0; - bool ext_mdio = FALSE; + bool ext_mdio = false; DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); @@ -138,7 +138,7 @@ static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) * e1000_init_phy_params_82575 - Init PHY func ptrs. * @hw: pointer to the HW structure **/ -static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) +STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val = E1000_SUCCESS; @@ -202,7 +202,8 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) if (phy->id == I347AT4_E_PHY_ID || phy->id == M88E1112_E_PHY_ID || phy->id == M88E1340M_E_PHY_ID) - phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; + phy->ops.get_cable_length = + e1000_get_cable_length_m88_gen2; else phy->ops.get_cable_length = e1000_get_cable_length_m88; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; @@ -221,7 +222,8 @@ static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) case I350_I_PHY_ID: phy->type = e1000_phy_82580; phy->ops.check_polarity = e1000_check_polarity_82577; - phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; + phy->ops.force_speed_duplex = + e1000_phy_force_speed_duplex_82577; phy->ops.get_cable_length = e1000_get_cable_length_82577; phy->ops.get_info = e1000_get_phy_info_82577; phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; @@ -270,7 +272,8 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) break; default: nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; - nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? + 16 : 8; break; } @@ -292,7 +295,7 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) nvm->ops.update = e1000_update_nvm_checksum_generic; nvm->ops.valid_led_default = e1000_valid_led_default_82575; - /* override genric family function pointers for specific descendants */ + /* override generic family function pointers for specific descendants */ switch (hw->mac.type) { case e1000_82580: nvm->ops.validate = e1000_validate_nvm_checksum_82580; @@ -313,7 +316,7 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) * e1000_init_mac_params_82575 - Init MAC func ptrs. * @hw: pointer to the HW structure **/ -static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) +STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; @@ -358,17 +361,16 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) if (mac->type == e1000_i350) { mac->rar_entry_count = E1000_RAR_ENTRIES_I350; /* Enable EEE default settings for i350 */ - dev_spec->eee_disable = FALSE; + dev_spec->eee_disable = false; } /* Set if part includes ASF firmware */ - mac->asf_firmware_present = TRUE; + mac->asf_firmware_present = true; /* FWSM register */ - mac->has_fwsm = TRUE; + mac->has_fwsm = true; /* ARC supported; valid only if manageability features are enabled. */ mac->arc_subsystem_valid = - (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) - ? TRUE : FALSE; + !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); /* Function pointers */ @@ -386,8 +388,7 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) /* physical interface link setup */ mac->ops.setup_physical_interface = (hw->phy.media_type == e1000_media_type_copper) - ? e1000_setup_copper_link_82575 - : e1000_setup_serdes_link_82575; + ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; /* physical interface shutdown */ mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; /* physical interface power up */ @@ -450,7 +451,7 @@ void e1000_init_function_pointers_82575(struct e1000_hw *hw) * * Acquire access rights to the correct PHY. **/ -static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) +STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw) { u16 mask = E1000_SWFW_PHY0_SM; @@ -472,7 +473,7 @@ static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) * * A wrapper to release access rights to the correct PHY. **/ -static void e1000_release_phy_82575(struct e1000_hw *hw) +STATIC void e1000_release_phy_82575(struct e1000_hw *hw) { u16 mask = E1000_SWFW_PHY0_SM; @@ -497,7 +498,7 @@ static void e1000_release_phy_82575(struct e1000_hw *hw) * Reads the PHY register at offset using the serial gigabit media independent * interface and stores the retrieved information in data. **/ -static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, +STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data) { s32 ret_val = -E1000_ERR_PARAM; @@ -530,7 +531,7 @@ out: * Writes the data to PHY register at the offset using the serial gigabit * media independent interface. **/ -static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, +STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data) { s32 ret_val = -E1000_ERR_PARAM; @@ -561,7 +562,7 @@ out: * Retrieves the PHY address and ID for both PHY's which do and do not use * sgmi interface. **/ -static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) +STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val = E1000_SUCCESS; @@ -622,8 +623,7 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); if (ret_val == E1000_SUCCESS) { DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", - phy_id, - phy->addr); + phy_id, phy->addr); /* * At the time of this writing, The M88 part is * the only supported SGMII PHY product. @@ -657,14 +657,14 @@ out: * * Resets the PHY using the serial gigabit media independent interface. **/ -static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) +STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); /* - * This isn't a TRUE "hard" reset, but is the only reset + * This isn't a true "hard" reset, but is the only reset * available to us at this time. */ @@ -690,7 +690,7 @@ out: /** * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state * @hw: pointer to the HW structure - * @active: TRUE to enable LPLU, FALSE to disable + * @active: true to enable LPLU, false to disable * * Sets the LPLU D0 state according to the active flag. When * activating LPLU this function also disables smart speed @@ -700,7 +700,7 @@ out: * This is a function pointer entry point only called by * PHY setup routines. **/ -static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) +STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val = E1000_SUCCESS; @@ -776,7 +776,7 @@ out: /** * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state * @hw: pointer to the HW structure - * @active: TRUE to enable LPLU, FALSE to disable + * @active: true to enable LPLU, false to disable * * Sets the LPLU D0 state according to the active flag. When * activating LPLU this function also disables smart speed @@ -786,7 +786,7 @@ out: * This is a function pointer entry point only called by * PHY setup routines. **/ -static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) +STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val = E1000_SUCCESS; @@ -810,12 +810,11 @@ static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) * important. During driver activity we should enable * SmartSpeed, so performance is maintained. */ - if (phy->smart_speed == e1000_smart_speed_on) { + if (phy->smart_speed == e1000_smart_speed_on) data |= E1000_82580_PM_SPD; - } else if (phy->smart_speed == e1000_smart_speed_off) { + else if (phy->smart_speed == e1000_smart_speed_off) data &= ~E1000_82580_PM_SPD; } - } E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); return ret_val; @@ -829,7 +828,7 @@ static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) * Success returns 0, Failure returns 1 * * The low power link up (lplu) state is set to the power management level D3 - * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 + * and SmartSpeed is disabled when active is true, else clear lplu for D3 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU * is used during Dx states where the power conservation is most important. * During driver activity, SmartSpeed should be enabled so performance is @@ -853,11 +852,10 @@ s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) * important. During driver activity we should enable * SmartSpeed, so performance is maintained. */ - if (phy->smart_speed == e1000_smart_speed_on) { + if (phy->smart_speed == e1000_smart_speed_on) data |= E1000_82580_PM_SPD; - } else if (phy->smart_speed == e1000_smart_speed_off) { + else if (phy->smart_speed == e1000_smart_speed_off) data &= ~E1000_82580_PM_SPD; - } } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { @@ -879,7 +877,7 @@ s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) * Return successful if access grant bit set, else clear the request for * EEPROM access and return -E1000_ERR_NVM (-1). **/ -static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) +STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) { s32 ret_val; @@ -900,8 +898,7 @@ static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) /* Clear all access error flags */ E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_ERROR_CLR); - DEBUGOUT("Nvm bit banging access error" - " detected and cleared.\n"); + DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); } } if (hw->mac.type == e1000_82580) { @@ -910,11 +907,11 @@ static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) /* Clear access error flag */ E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_BLOCKED); - DEBUGOUT("Nvm bit banging access" - " error detected and cleared.\n"); + DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); } } + ret_val = e1000_acquire_nvm_generic(hw); if (ret_val) e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); @@ -930,7 +927,7 @@ out: * Stop any current commands to the EEPROM and clear the EEPROM request bit, * then release the semaphores acquired. **/ -static void e1000_release_nvm_82575(struct e1000_hw *hw) +STATIC void e1000_release_nvm_82575(struct e1000_hw *hw) { DEBUGFUNC("e1000_release_nvm_82575"); @@ -945,7 +942,7 @@ static void e1000_release_nvm_82575(struct e1000_hw *hw) * Acquire the SW/FW semaphore to access the PHY or NVM. The mask * will also specify which port we're acquiring the lock for. **/ -static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) +STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) { u32 swfw_sync; u32 swmask = mask; @@ -997,14 +994,14 @@ out: * Release the SW/FW semaphore used to access the PHY or NVM. The mask * will also specify which port we're releasing the lock for. **/ -static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) +STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) { u32 swfw_sync; DEBUGFUNC("e1000_release_swfw_sync_82575"); - while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); - /* Empty */ + while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) + ; /* Empty */ swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); swfw_sync &= ~mask; @@ -1023,7 +1020,7 @@ static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon * would not be able to be reset or change link. **/ -static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) +STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) { s32 timeout = PHY_CFG_TIMEOUT; s32 ret_val = E1000_SUCCESS; @@ -1047,7 +1044,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) DEBUGOUT("MNG configuration cycle has not completed.\n"); /* If EEPROM is not marked present, init the PHY manually */ - if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && (hw->phy.type == e1000_phy_igp_3)) e1000_phy_init_script_igp3(hw); @@ -1064,7 +1061,7 @@ static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) * interface, use PCS to retrieve the link speed and duplex information. * Otherwise, use the generic function to get the link speed and duplex info. **/ -static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, +STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex) { s32 ret_val; @@ -1088,7 +1085,7 @@ static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, * If sgmii is enabled, then use the pcs register to determine link, otherwise * use the generic interface for determining link. **/ -static s32 e1000_check_for_link_82575(struct e1000_hw *hw) +STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw) { s32 ret_val; u16 speed, duplex; @@ -1115,7 +1112,7 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw) * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown * @hw: pointer to the HW structure **/ -static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) +STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) { u32 reg; @@ -1178,21 +1175,19 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, mac->serdes_has_link = TRUE; /* Detect and store PCS speed */ - if (pcs & E1000_PCS_LSTS_SPEED_1000) { + if (pcs & E1000_PCS_LSTS_SPEED_1000) *speed = SPEED_1000; - } else if (pcs & E1000_PCS_LSTS_SPEED_100) { + else if (pcs & E1000_PCS_LSTS_SPEED_100) *speed = SPEED_100; - } else { + else *speed = SPEED_10; - } /* Detect and store PCS duplex */ - if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { + if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) *duplex = FULL_DUPLEX; - } else { + else *duplex = HALF_DUPLEX; } - } return E1000_SUCCESS; } @@ -1239,7 +1234,7 @@ void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) * * This resets the hardware into a known state. **/ -static s32 e1000_reset_hw_82575(struct e1000_hw *hw) +STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw) { u32 ctrl; s32 ret_val; @@ -1251,15 +1246,13 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw) * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000_disable_pcie_master_generic(hw); - if (ret_val) { + if (ret_val) DEBUGOUT("PCI-E Master disable polling has failed.\n"); - } /* set the completion timeout for interface */ ret_val = e1000_set_pcie_completion_timeout(hw); - if (ret_val) { + if (ret_val) DEBUGOUT("PCI-E Set completion timeout has failed.\n"); - } DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); @@ -1286,7 +1279,7 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw) } /* If EEPROM is not present, run manual init scripts */ - if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) e1000_reset_init_script_82575(hw); /* Clear any pending interrupt events. */ @@ -1305,7 +1298,7 @@ static s32 e1000_reset_hw_82575(struct e1000_hw *hw) * * This inits the hardware readying it for operation. **/ -static s32 e1000_init_hw_82575(struct e1000_hw *hw) +STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; s32 ret_val; @@ -1359,7 +1352,7 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw) * for link, once link is established calls to configure collision distance * and flow control are called. **/ -static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) +STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) { u32 ctrl; s32 ret_val; @@ -1422,7 +1415,7 @@ out: * interface (sgmii), or serdes fiber is being used. Configures the link * for auto-negotiation or forces speed/duplex. **/ -static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) +STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) { u32 ctrl_ext, ctrl_reg, reg; bool pcs_autoneg; @@ -1461,13 +1454,13 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { case E1000_CTRL_EXT_LINK_MODE_SGMII: /* sgmii mode lets the phy handle forcing speed/duplex */ - pcs_autoneg = TRUE; + pcs_autoneg = true; /* autoneg time out should be disabled for SGMII mode */ reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); break; case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: /* disable PCS autoneg and support parallel detect only */ - pcs_autoneg = FALSE; + pcs_autoneg = false; /* fall through to default case */ default: /* @@ -1527,7 +1520,7 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) * Read the EEPROM for the current default LED configuration. If the * LED configuration is not valid, set to a valid LED configuration. **/ -static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) +STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) { s32 ret_val; @@ -1540,7 +1533,7 @@ static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) } if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { - switch(hw->phy.media_type) { + switch (hw->phy.media_type) { case e1000_media_type_internal_serdes: *data = ID_LED_DEFAULT_82575_SERDES; break; @@ -1575,7 +1568,7 @@ static bool e1000_sgmii_active_82575(struct e1000_hw *hw) * Inits recommended HW defaults after a reset when there is no EEPROM * detected. This is only for the 82575. **/ -static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) +STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw) { DEBUGFUNC("e1000_reset_init_script_82575"); @@ -1610,7 +1603,7 @@ static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) * e1000_read_mac_addr_82575 - Read device MAC address * @hw: pointer to the HW structure **/ -static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) +STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; @@ -1638,7 +1631,7 @@ out: * Configures the collision distance to the default value and is used * during link setup. **/ -static void e1000_config_collision_dist_82575(struct e1000_hw *hw) +STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw) { u32 tctl_ext; @@ -1660,7 +1653,7 @@ static void e1000_config_collision_dist_82575(struct e1000_hw *hw) * In the case of a PHY power down to save power, or to turn off link during a * driver unload, or wake on lan is not enabled, remove the link. **/ -static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) +STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; @@ -1680,7 +1673,7 @@ static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) * * Clears the hardware counters by reading the counter registers. **/ -static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) +STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) { DEBUGFUNC("e1000_clear_hw_cntrs_82575"); @@ -1823,7 +1816,7 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) * increase the value to either 10ms to 200ms for capability version 1 config, * or 16ms to 55ms for version 2. **/ -static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) +STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) { u32 gcr = E1000_READ_REG(hw, E1000_GCR); s32 ret_val = E1000_SUCCESS; @@ -1974,7 +1967,7 @@ void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) * Reads the MDI control register in the PHY at offset and stores the * information read to data. **/ -static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) +STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) { s32 ret_val; @@ -2000,7 +1993,7 @@ out: * * Writes data to MDI control register in the PHY at offset. **/ -static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) +STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) { s32 ret_val; @@ -2026,7 +2019,7 @@ out: * the values found in the EEPROM. This addresses an issue in which these * bits are not restored from EEPROM after reset. **/ -static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) +STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; u32 mdicnfg; @@ -2064,7 +2057,7 @@ out: * This resets function or entire device (all ports, etc.) * to a known state. **/ -static s32 e1000_reset_hw_82580(struct e1000_hw *hw) +STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; /* BH SW mailbox bit in SW_FW_SYNC */ @@ -2074,7 +2067,7 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw) DEBUGFUNC("e1000_reset_hw_82580"); - hw->dev_spec._82575.global_device_reset = FALSE; + hw->dev_spec._82575.global_device_reset = false; /* Get current control state. */ ctrl = E1000_READ_REG(hw, E1000_CTRL); @@ -2123,7 +2116,7 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw) } /* If EEPROM is not present, run manual init scripts */ - if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) e1000_reset_init_script_82575(hw); /* clear global device reset status bit */ @@ -2247,7 +2240,7 @@ out: * the EEPROM and then verifies that the sum of the EEPROM is * equal to 0xBABA. **/ -static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) +STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; u16 eeprom_regions_count = 1; @@ -2288,7 +2281,7 @@ out: * each word of the EEPROM up to the checksum. Then calculates the EEPROM * checksum and writes the value to the EEPROM. **/ -static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) +STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) { s32 ret_val; u16 j, nvm_data; @@ -2298,19 +2291,17 @@ static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); if (ret_val) { - DEBUGOUT("NVM Read Error while updating checksum" - " compatibility bit.\n"); + DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); goto out; } - if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { + if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { /* set compatibility bit to validate checksums appropriately */ nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); if (ret_val) { - DEBUGOUT("NVM Write Error while updating checksum" - " compatibility bit.\n"); + DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); goto out; } } @@ -2318,10 +2309,9 @@ static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) for (j = 0; j < 4; j++) { nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); - if (ret_val) { + if (ret_val) goto out; } - } out: return ret_val; @@ -2335,7 +2325,7 @@ out: * the EEPROM and then verifies that the sum of the EEPROM is * equal to 0xBABA. **/ -static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) +STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; u16 j; @@ -2363,7 +2353,7 @@ out: * each word of the EEPROM up to the checksum. Then calculates the EEPROM * checksum and writes the value to the EEPROM. **/ -static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) +STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; u16 j; @@ -2405,17 +2395,13 @@ s32 e1000_set_eee_i350(struct e1000_hw *hw) /* enable or disable per user setting */ if (!(hw->dev_spec._82575.eee_disable)) { - ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | - E1000_IPCNFG_EEE_100M_AN); - eeer |= (E1000_EEER_TX_LPI_EN | - E1000_EEER_RX_LPI_EN | + ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); + eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | E1000_EEER_LPI_FC); } else { - ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | - E1000_IPCNFG_EEE_100M_AN); - eeer &= ~(E1000_EEER_TX_LPI_EN | - E1000_EEER_RX_LPI_EN | + ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); + eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | E1000_EEER_LPI_FC); } E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); diff --git a/lib/librte_pmd_e1000/e1000/e1000_82575.h b/lib/librte_pmd_e1000/e1000/e1000_82575.h index 1b66ba13ea..f0857d444a 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_82575.h +++ b/lib/librte_pmd_e1000/e1000/e1000_82575.h @@ -62,19 +62,19 @@ struct e1000_adv_data_desc { union { u32 data; struct { - u32 datalen :16; /* Data buffer length */ - u32 rsvd :4; - u32 dtyp :4; /* Descriptor type */ - u32 dcmd :8; /* Descriptor command */ + u32 datalen:16; /* Data buffer length */ + u32 rsvd:4; + u32 dtyp:4; /* Descriptor type */ + u32 dcmd:8; /* Descriptor command */ } config; } lower; union { u32 data; struct { - u32 status :4; /* Descriptor status */ - u32 idx :4; - u32 popts :6; /* Packet Options */ - u32 paylen :18; /* Payload length */ + u32 status:4; /* Descriptor status */ + u32 idx:4; + u32 popts:6; /* Packet Options */ + u32 paylen:18; /* Payload length */ } options; } upper; }; @@ -99,23 +99,23 @@ struct e1000_adv_context_desc { union { u32 ip_config; struct { - u32 iplen :9; - u32 maclen :7; - u32 vlan_tag :16; + u32 iplen:9; + u32 maclen:7; + u32 vlan_tag:16; } fields; } ip_setup; u32 seq_num; union { u64 l4_config; struct { - u32 mkrloc :9; - u32 tucmd :11; - u32 dtyp :4; - u32 adv :8; - u32 rsvd :4; - u32 idx :4; - u32 l4len :8; - u32 mss :16; + u32 mkrloc:9; + u32 tucmd:11; + u32 dtyp:4; + u32 adv:8; + u32 rsvd:4; + u32 idx:4; + u32 l4len:8; + u32 mss:16; } fields; } l4_setup; }; @@ -150,7 +150,8 @@ struct e1000_adv_context_desc { #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 -#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT) +#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ + E1000_VMRCTL_MIRROR_PORT_SHIFT) #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) @@ -298,14 +299,15 @@ union e1000_adv_tx_desc { #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ -#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on packet */ -#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ -#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ +#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ +#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ +#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ -#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/ +/* 1st & Last TSO-full iSCSI PDU*/ +#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ @@ -327,7 +329,8 @@ struct e1000_adv_tx_context_desc { #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ /* IPSec Encrypt Enable for ESP */ #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 -#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ +/* Req requires Markers and CRC */ +#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ /* Adv ctxt IPSec SA IDX mask */ @@ -336,14 +339,14 @@ struct e1000_adv_tx_context_desc { #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF /* Additional Transmit Descriptor Control definitions */ -#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ -#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ +#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ +#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ /* Tx Queue Arbitration Priority 0=low, 1=high */ #define E1000_TXDCTL_PRIORITY 0x08000000 /* Additional Receive Descriptor Control definitions */ -#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ -#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ +#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ +#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ /* Direct Cache Access (DCA) definitions */ #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ @@ -354,8 +357,8 @@ struct e1000_adv_tx_context_desc { #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ -#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ -#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ +#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ +#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ @@ -395,10 +398,10 @@ struct e1000_adv_tx_context_desc { #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 #define E1000_NVM_APME_82575 0x0400 -#define MAX_NUM_VFS 8 +#define MAX_NUM_VFS 7 -#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */ -#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ +#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ +#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 #define E1000_DTXSWC_LLE_SHIFT 16 @@ -461,6 +464,8 @@ struct e1000_adv_tx_context_desc { #define E1000_DTXCTL_MDP_EN 0x0020 #define E1000_DTXCTL_SPOOF_INT 0x0040 +#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) + #define ALL_QUEUES 0xFFFF /* Rx packet buffer size defines */ diff --git a/lib/librte_pmd_e1000/e1000/e1000_api.c b/lib/librte_pmd_e1000/e1000/e1000_api.c index cb7a48ce3f..3b18f1f75f 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_api.c +++ b/lib/librte_pmd_e1000/e1000/e1000_api.c @@ -206,10 +206,10 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) /** * e1000_setup_init_funcs - Initializes function pointers * @hw: pointer to the HW structure - * @init_device: TRUE will initialize the rest of the function pointers - * getting the device ready for use. FALSE will only set + * @init_device: true will initialize the rest of the function pointers + * getting the device ready for use. false will only set * MAC type and the function pointers for the other init - * functions. Passing FALSE will not generate any hardware + * functions. Passing false will not generate any hardware * reads or writes. * * This function must be called by a driver in order to use the rest @@ -393,7 +393,7 @@ bool e1000_check_mng_mode(struct e1000_hw *hw) if (hw->mac.ops.check_mng_mode) return hw->mac.ops.check_mng_mode(hw); - return FALSE; + return false; } /** @@ -683,7 +683,7 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) * It also does alignment considerations to do the writes in most efficient * way. Also fills up the sum of the buffer in *buffer parameter. **/ -s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length, +s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum) { if (hw->mac.ops.mng_host_if_write) @@ -719,7 +719,7 @@ s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, * and also checks whether the previous command is completed. It busy waits * in case of previous command is not completed. **/ -s32 e1000_mng_enable_host_if(struct e1000_hw * hw) +s32 e1000_mng_enable_host_if(struct e1000_hw *hw) { if (hw->mac.ops.mng_enable_host_if) return hw->mac.ops.mng_enable_host_if(hw); @@ -919,7 +919,7 @@ s32 e1000_phy_commit(struct e1000_hw *hw) * Success returns 0, Failure returns 1 * * The low power link up (lplu) state is set to the power management level D0 - * and SmartSpeed is disabled when active is TRUE, else clear lplu for D0 + * and SmartSpeed is disabled when active is true, else clear lplu for D0 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU * is used during Dx states where the power conservation is most important. * During driver activity, SmartSpeed should be enabled so performance is @@ -941,7 +941,7 @@ s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) * Success returns 0, Failure returns 1 * * The low power link up (lplu) state is set to the power management level D3 - * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 + * and SmartSpeed is disabled when active is true, else clear lplu for D3 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU * is used during Dx states where the power conservation is most important. * During driver activity, SmartSpeed should be enabled so performance is diff --git a/lib/librte_pmd_e1000/e1000/e1000_api.h b/lib/librte_pmd_e1000/e1000/e1000_api.h index 1e51d1d136..9a1e5c75e0 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_api.h +++ b/lib/librte_pmd_e1000/e1000/e1000_api.h @@ -56,14 +56,13 @@ s32 e1000_check_for_link(struct e1000_hw *hw); s32 e1000_reset_hw(struct e1000_hw *hw); s32 e1000_init_hw(struct e1000_hw *hw); s32 e1000_setup_link(struct e1000_hw *hw); -s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, - u16 *duplex); +s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); s32 e1000_disable_pcie_master(struct e1000_hw *hw); void e1000_config_collision_dist(struct e1000_hw *hw); void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); -void e1000_update_mc_addr_list(struct e1000_hw *hw, - u8 *mc_addr_list, u32 mc_addr_count); +void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list, + u32 mc_addr_count); s32 e1000_setup_led(struct e1000_hw *hw); s32 e1000_cleanup_led(struct e1000_hw *hw); s32 e1000_check_reset_block(struct e1000_hw *hw); @@ -77,8 +76,8 @@ s32 e1000_get_cable_length(struct e1000_hw *hw); s32 e1000_validate_mdi_setting(struct e1000_hw *hw); s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data); -s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, - u32 offset, u8 data); +s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset, + u8 data); s32 e1000_get_phy_info(struct e1000_hw *hw); void e1000_release_phy(struct e1000_hw *hw); s32 e1000_acquire_phy(struct e1000_hw *hw); @@ -87,8 +86,7 @@ s32 e1000_phy_commit(struct e1000_hw *hw); void e1000_power_up_phy(struct e1000_hw *hw); void e1000_power_down_phy(struct e1000_hw *hw); s32 e1000_read_mac_addr(struct e1000_hw *hw); -s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, - u32 pba_num_size); +s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size); s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size); void e1000_reload_nvm(struct e1000_hw *hw); s32 e1000_update_nvm_checksum(struct e1000_hw *hw); @@ -96,20 +94,18 @@ s32 e1000_validate_nvm_checksum(struct e1000_hw *hw); s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); -s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, - u16 *data); +s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_wait_autoneg(struct e1000_hw *hw); s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); bool e1000_check_mng_mode(struct e1000_hw *hw); bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); s32 e1000_mng_enable_host_if(struct e1000_hw *hw); -s32 e1000_mng_host_if_write(struct e1000_hw *hw, - u8 *buffer, u16 length, u16 offset, u8 *sum); +s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, + u16 offset, u8 *sum); s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, struct e1000_host_mng_command_header *hdr); -s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, - u8 *buffer, u16 length); +s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); /* * TBI_ACCEPT macro definition: @@ -130,11 +126,11 @@ s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, * Typical use: * ... * if (TBI_ACCEPT) { - * accept_frame = TRUE; + * accept_frame = true; * e1000_tbi_adjust_stats(adapter, MacAddress); * frame_length--; * } else { - * accept_frame = FALSE; + * accept_frame = false; * } * ... */ @@ -142,7 +138,8 @@ s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, /* The carrier extension symbol, as received by the NIC. */ #define CARRIER_EXTENSION 0x0F -#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \ +#define TBI_ACCEPT(a, status, errors, length, last_byte, \ + min_frame_size, max_frame_size) \ (e1000_tbi_sbp_enabled_82543(a) && \ (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ ((last_byte) == CARRIER_EXTENSION) && \ @@ -152,4 +149,3 @@ s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, (((length) > min_frame_size) && \ ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1))))) -#endif diff --git a/lib/librte_pmd_e1000/e1000/e1000_defines.h b/lib/librte_pmd_e1000/e1000/e1000_defines.h index 5a96601f45..1cc0fcb1a8 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_defines.h +++ b/lib/librte_pmd_e1000/e1000/e1000_defines.h @@ -113,11 +113,11 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ /* Reserved (bits 4,5) in >= 82575 */ -#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ -#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */ #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA -#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ -#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ +#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ @@ -130,7 +130,7 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_CTRL_EXT_PFRSTD 0x00004000 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ -#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ +#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/ #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 @@ -148,13 +148,13 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ -#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ +#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ /* IAME enable bit (27) was removed in >= 82575 */ -#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */ -#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error - * detection enabled */ -#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity - * error detection enable */ +#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ +/* packet buffer parity error detection enabled */ +#define E1000_CRTL_EXT_PB_PAREN 0x01000000 +/* descriptor FIFO parity error detection enable */ +#define E1000_CTRL_EXT_DF_PAREN 0x02000000 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ #define E1000_I2CCMD_REG_ADDR_SHIFT 16 @@ -265,8 +265,8 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable IP address filtering */ #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 -#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ -#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ +#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */ +#define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */ #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ @@ -274,7 +274,7 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ #define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */ -#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabled or not */ +#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */ #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ @@ -383,12 +383,12 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ -#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock - * indication in SDP[0] */ -#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through - * PHYRST_N pin */ -#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external - * LINK_0 and LINK_1 pins */ +/* Defined polarity of Dock/Undock indication in SDP[0] */ +#define E1000_CTRL_D_UD_POLARITY 0x00004000 +/* Reset both PHY ports, through PHYRST_N pin */ +#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 +/* enable link status from external LINK_0 and LINK_1 pins */ +#define E1000_CTRL_EXT_LINK_EN 0x00010000 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ @@ -454,7 +454,7 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 /* Device Status */ -#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ #define E1000_STATUS_FUNC_SHIFT 2 @@ -466,33 +466,33 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ -#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ +#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ -#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. - * Clear on write '0'. */ +/* Change in Dock/Undock state clear on write '0'. */ +#define E1000_STATUS_DOCK_CI 0x00000800 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ -#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ +#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */ #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ -#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution - * disabled */ +/* BMC external code execution disabled */ +#define E1000_STATUS_BMC_LITE 0x01000000 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ #define E1000_STATUS_FUSE_8 0x04000000 #define E1000_STATUS_FUSE_9 0x08000000 -#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ -#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ +#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */ +#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */ /* Constants used to interpret the masked PCI-X bus speed. */ -#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ -#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ -#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/ +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ #define SPEED_10 10 #define SPEED_100 100 @@ -510,15 +510,16 @@ POSSIBILITY OF SUCH DAMAGE. #define ADVERTISE_1000_FULL 0x0020 /* 1000/H is not supported, nor spec-compliant. */ -#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ - ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ - ADVERTISE_1000_FULL) -#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ - ADVERTISE_100_HALF | ADVERTISE_100_FULL) +#define E1000_ALL_SPEED_DUPLEX ( \ + ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ + ADVERTISE_100_FULL | ADVERTISE_1000_FULL) +#define E1000_ALL_NOT_GIG ( \ + ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ + ADVERTISE_100_FULL) #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) -#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ - ADVERTISE_1000_FULL) +#define E1000_ALL_FULL_DUPLEX ( \ + ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX @@ -573,7 +574,7 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ -#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ +#define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ @@ -737,8 +738,8 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_ICR_MNG 0x00040000 /* Manageability event */ #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ -#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver - * should claim the interrupt */ +/* If this bit asserted, the driver should claim the interrupt */ +#define E1000_ICR_INT_ASSERTED 0x80000000 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ @@ -746,10 +747,10 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ -#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW - * bit in the FWSM */ -#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates - * an interrupt */ +/* FW changed the status of DISSW bit in the FWSM */ +#define E1000_ICR_DSW 0x00000020 +/* LAN connected device generates an interrupt */ +#define E1000_ICR_PHYINT 0x00001000 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ #define E1000_ICR_FER 0x00400000 /* Fatal Error */ @@ -821,18 +822,18 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ -#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO - * parity error */ -#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO - * parity error */ -#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer - * parity error */ -#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity - * error */ -#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO - * parity error */ -#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO - * parity error */ +/* Q0 Rx desc FIFO parity error */ +#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 +/* Q0 Tx desc FIFO parity error */ +#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 +/* host arb read buffer parity error */ +#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR +/* packet buffer parity error */ +#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR +/* Q1 Rx desc FIFO parity error */ +#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 +/* Q1 Tx desc FIFO parity error */ +#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 #define E1000_IMS_DSW E1000_ICR_DSW #define E1000_IMS_PHYINT E1000_ICR_PHYINT #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ @@ -873,18 +874,18 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ -#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO - * parity error */ -#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO - * parity error */ -#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer - * parity error */ -#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity - * error */ -#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO - * parity error */ -#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO - * parity error */ +/* Q0 Rx desc FIFO parity error */ +#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 +/* Q0 Tx desc FIFO parity error */ +#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 +/* host arb read buffer parity error */ +#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR +/* packet buffer parity error */ +#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR +/* Q1 Rx desc FIFO parity error */ +#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 +/* Q1 Tx desc FIFO parity error */ +#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 #define E1000_ICS_DSW E1000_ICR_DSW #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ #define E1000_ICS_PHYINT E1000_ICR_PHYINT @@ -1063,16 +1064,16 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ -#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ +#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ -/* Powerville EEE defines */ -#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Enable 1G AN */ -#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Enable 100M AN */ +/* I350 EEE defines */ +#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ +#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ -#define E1000_EEER_LPI_FC 0x00040000 /* EEER Enable on Flow Control*/ +#define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ /* EEE status */ -#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability negotiated */ +#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ @@ -1141,34 +1142,34 @@ POSSIBILITY OF SUCH DAMAGE. /* Link Partner Ability Register (Base Page) */ #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ -#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ -#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ -#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ -#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ -#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ -#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ -#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ /* Autoneg Expansion Register */ #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ -#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ -#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ -#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ -#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ /* 1000BASE-T Control Register */ #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ -#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ - /* 0=DTE device */ -#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ - /* 0=Configure PHY as Slave */ -#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ - /* 0=Automatic Master/Slave config */ +/* 1=Repeater/switch device port 0=DTE device */ +#define CR_1000T_REPEATER_DTE 0x0400 +/* 1=Configure PHY as Master 0=Configure PHY as Slave */ +#define CR_1000T_MS_VALUE 0x0800 +/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ +#define CR_1000T_MS_ENABLE 0x1000 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ @@ -1176,13 +1177,13 @@ POSSIBILITY OF SUCH DAMAGE. #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ /* 1000BASE-T Status Register */ -#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ -#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ -#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 @@ -1234,7 +1235,7 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ -#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ +#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ #define E1000_EECD_SECVAL_SHIFT 22 @@ -1279,7 +1280,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Mask bits for fields in Word 0x24 of the NVM */ #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ -#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ +#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ /* Mask bits for fields in Word 0x0f of the NVM */ #define NVM_WORD0F_PAUSE_MASK 0x3000 @@ -1414,16 +1415,16 @@ POSSIBILITY OF SUCH DAMAGE. #define M88_VENDOR 0x0141 /* M88E1000 Specific Registers */ -#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ -#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ -#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ -#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ -#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ -#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ -#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ +#define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ @@ -1433,8 +1434,8 @@ POSSIBILITY OF SUCH DAMAGE. #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ /* 1=CLK125 low, 0=CLK125 toggling */ #define M88E1000_PSCR_CLK125_DISABLE 0x0010 -#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ - /* Manual MDI configuration */ +/* MDI Crossover Mode bits 6:5 Manual MDI configuration */ +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ #define M88E1000_PSCR_AUTO_X_1000T 0x0040 @@ -1515,7 +1516,6 @@ POSSIBILITY OF SUCH DAMAGE. #define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F /* Intel I347AT4 Registers */ - #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ #define I347AT4_PAGE_SELECT 0x16 @@ -1565,68 +1565,47 @@ POSSIBILITY OF SUCH DAMAGE. #define GG82563_MIN_ALT_REG 30 /* GG82563 Specific Registers */ -#define GG82563_PHY_SPEC_CTRL \ - GG82563_REG(0, 16) /* PHY Specific Control */ -#define GG82563_PHY_SPEC_STATUS \ - GG82563_REG(0, 17) /* PHY Specific Status */ -#define GG82563_PHY_INT_ENABLE \ - GG82563_REG(0, 18) /* Interrupt Enable */ -#define GG82563_PHY_SPEC_STATUS_2 \ - GG82563_REG(0, 19) /* PHY Specific Status 2 */ -#define GG82563_PHY_RX_ERR_CNTR \ - GG82563_REG(0, 21) /* Receive Error Counter */ -#define GG82563_PHY_PAGE_SELECT \ - GG82563_REG(0, 22) /* Page Select */ -#define GG82563_PHY_SPEC_CTRL_2 \ - GG82563_REG(0, 26) /* PHY Specific Control 2 */ -#define GG82563_PHY_PAGE_SELECT_ALT \ - GG82563_REG(0, 29) /* Alternate Page Select */ -#define GG82563_PHY_TEST_CLK_CTRL \ - GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ - -#define GG82563_PHY_MAC_SPEC_CTRL \ - GG82563_REG(2, 21) /* MAC Specific Control Register */ -#define GG82563_PHY_MAC_SPEC_CTRL_2 \ - GG82563_REG(2, 26) /* MAC Specific Control 2 */ - -#define GG82563_PHY_DSP_DISTANCE \ - GG82563_REG(5, 26) /* DSP Distance */ +#define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ +#define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */ +#define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */ +#define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */ +#define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */ +#define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ +#define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ +#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ +/* Test Clock Control (use reg. 29 to select) */ +#define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) + +/* MAC Specific Control Register */ +#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) +#define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */ + +#define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ /* Page 193 - Port Control Registers */ -#define GG82563_PHY_KMRN_MODE_CTRL \ - GG82563_REG(193, 16) /* Kumeran Mode Control */ -#define GG82563_PHY_PORT_RESET \ - GG82563_REG(193, 17) /* Port Reset */ -#define GG82563_PHY_REVISION_ID \ - GG82563_REG(193, 18) /* Revision ID */ -#define GG82563_PHY_DEVICE_ID \ - GG82563_REG(193, 19) /* Device ID */ -#define GG82563_PHY_PWR_MGMT_CTRL \ - GG82563_REG(193, 20) /* Power Management Control */ -#define GG82563_PHY_RATE_ADAPT_CTRL \ - GG82563_REG(193, 25) /* Rate Adaptation Control */ +/* Kumeran Mode Control */ +#define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) +#define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */ +#define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */ +#define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */ +#define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ +/* Rate Adaptation Control */ +#define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) /* Page 194 - KMRN Registers */ -#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ - GG82563_REG(194, 16) /* FIFO's Control/Status */ -#define GG82563_PHY_KMRN_CTRL \ - GG82563_REG(194, 17) /* Control */ -#define GG82563_PHY_INBAND_CTRL \ - GG82563_REG(194, 18) /* Inband Control */ -#define GG82563_PHY_KMRN_DIAGNOSTIC \ - GG82563_REG(194, 19) /* Diagnostic */ -#define GG82563_PHY_ACK_TIMEOUTS \ - GG82563_REG(194, 20) /* Acknowledge Timeouts */ -#define GG82563_PHY_ADV_ABILITY \ - GG82563_REG(194, 21) /* Advertised Ability */ -#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ - GG82563_REG(194, 23) /* Link Partner Advertised Ability */ -#define GG82563_PHY_ADV_NEXT_PAGE \ - GG82563_REG(194, 24) /* Advertised Next Page */ -#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ - GG82563_REG(194, 25) /* Link Partner Advertised Next page */ -#define GG82563_PHY_KMRN_MISC \ - GG82563_REG(194, 26) /* Misc. */ +/* FIFO's Control/Status */ +#define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) +#define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */ +#define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ +#define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */ +#define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */ +#define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */ +/* Link Partner Advertised Ability */ +#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23) +#define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */ +/* Link Partner Advertised Next page */ +#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25) +#define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */ /* MDI Control */ #define E1000_MDIC_DATA_MASK 0x0000FFFF @@ -1678,55 +1657,48 @@ POSSIBILITY OF SUCH DAMAGE. (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) /* DMA Coalescing register fields */ -#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing - * Watchdog Timer */ -#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Rx - * Threshold */ +/* DMA Coalescing Watchdog Timer */ +#define E1000_DMACR_DMACWT_MASK 0x00003FFF +/* DMA Coalescing Rx Threshold */ +#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 #define E1000_DMACR_DMACTHR_SHIFT 16 -#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe - * transactions */ +/* Lx when no PCIe transactions */ +#define E1000_DMACR_DMAC_LX_MASK 0x30000000 #define E1000_DMACR_DMAC_LX_SHIFT 28 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ -#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit - * Threshold */ +/* DMA Coalescing Transmit Threshold */ +#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ -#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate - * Threshold */ -#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx packet rate in - * current window */ +/* Rx Traffic Rate Threshold */ +#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF +/* Rx packet rate in current window */ +#define E1000_DMCRTRH_LRPRCW 0x80000000 -#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Traffic - * Current Cnt */ +/* DMA Coal Rx Traffic Current Count */ +#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF -#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rx Threshold - * High val */ +/* Flow ctrl Rx Threshold High val */ +#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 #define E1000_FCRTC_RTH_COAL_SHIFT 4 -#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based - on DMA coal */ +/* Lx power decision based on DMA coal */ +#define E1000_PCIEMISC_LX_DECISION 0x00000080 -/* Proxy Filer Control */ +/* Proxy Filter Control */ #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ -#define E1000_PROXYFC_MC 0x00000008 /* Directed Multicast - * Proxy */ +#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ -#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy - * Enable */ +#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ -#define E1000_PROXYFC_NS 0x00000200 /* IPv4 Neighborhood - * Solicitation */ -#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy - * Enable */ +#define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */ +#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ /* Proxy Status */ #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ /* Firmware Status */ -#define E1000_FWSTS_FWRI 0x80000000 /* Firmware Reset - * Indication */ - - +#define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ #endif /* _E1000_DEFINES_H_ */ diff --git a/lib/librte_pmd_e1000/e1000/e1000_hw.h b/lib/librte_pmd_e1000/e1000/e1000_hw.h index 365ebcf3a1..5110121bb1 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_hw.h +++ b/lib/librte_pmd_e1000/e1000/e1000_hw.h @@ -92,7 +92,7 @@ enum e1000_mac_type { e1000_i350, e1000_vfadapt, e1000_vfadapt_i350, - e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ + e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ }; enum e1000_media_type { diff --git a/lib/librte_pmd_e1000/e1000/e1000_mac.c b/lib/librte_pmd_e1000/e1000/e1000_mac.c index 8428a845b5..746cd748ba 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_mac.c +++ b/lib/librte_pmd_e1000/e1000/e1000_mac.c @@ -36,8 +36,8 @@ POSSIBILITY OF SUCH DAMAGE. static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); -static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); -static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); +STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); +STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); /** * e1000_init_mac_ops_generic - Initialize MAC function pointers @@ -115,13 +115,13 @@ s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) } /** - * e1000_null_mng_mode - No-op function, return FALSE + * e1000_null_mng_mode - No-op function, return false * @hw: pointer to the HW structure **/ bool e1000_null_mng_mode(struct e1000_hw *hw) { DEBUGFUNC("e1000_null_mng_mode"); - return FALSE; + return false; } /** @@ -228,8 +228,7 @@ s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) bus->type = e1000_bus_type_pci_express; - ret_val = e1000_read_pcie_cap_reg(hw, - PCIE_LINK_STATUS, + ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, &pcie_link_status); if (ret_val) { bus->width = e1000_bus_width_unknown; @@ -248,8 +247,7 @@ s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) } bus->width = (enum e1000_bus_width)((pcie_link_status & - PCIE_LINK_WIDTH_MASK) >> - PCIE_LINK_WIDTH_SHIFT); + PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); } mac->ops.set_lan_id(hw); @@ -265,7 +263,7 @@ s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) * Determines the LAN function id by reading memory-mapped registers * and swaps the port value if requested. **/ -static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) +STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) { struct e1000_bus_info *bus = &hw->bus; u32 reg; @@ -461,7 +459,7 @@ out: * Sets the receive address array register at index to the address passed * in by addr. **/ -void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) +STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) { u32 rar_low, rar_high; @@ -471,8 +469,7 @@ void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) * HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ - rar_low = ((u32) addr[0] | - ((u32) addr[1] << 8) | + rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); @@ -726,7 +723,7 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) if (!link) goto out; /* No link detected */ - mac->get_link_status = FALSE; + mac->get_link_status = false; /* * Check if there was DownShift, must be checked @@ -827,7 +824,7 @@ s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); - mac->serdes_has_link = TRUE; + mac->serdes_has_link = true; } out: @@ -895,7 +892,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); - mac->serdes_has_link = TRUE; + mac->serdes_has_link = true; } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { /* * If we force link for non-auto-negotiation switch, check @@ -907,11 +904,11 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) rxcw = E1000_READ_REG(hw, E1000_RXCW); if (rxcw & E1000_RXCW_SYNCH) { if (!(rxcw & E1000_RXCW_IV)) { - mac->serdes_has_link = TRUE; + mac->serdes_has_link = true; DEBUGOUT("SERDES: Link up - forced.\n"); } } else { - mac->serdes_has_link = FALSE; + mac->serdes_has_link = false; DEBUGOUT("SERDES: Link down - force failed.\n"); } } @@ -1105,7 +1102,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); /* - * If we have a signal (the cable is plugged in, or assumed TRUE for + * If we have a signal (the cable is plugged in, or assumed true for * serdes media) then poll for a "Link-Up" indication in the Device * Status Register. Time-out if a link isn't seen in 500 milliseconds * seconds (Auto-negotiation should complete in less than 500 @@ -1488,11 +1485,10 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) */ if (hw->fc.requested_mode == e1000_fc_full) { hw->fc.current_mode = e1000_fc_full; - DEBUGOUT("Flow Control = FULL.\r\n"); + DEBUGOUT("Flow Control = FULL.\n"); } else { hw->fc.current_mode = e1000_fc_rx_pause; - DEBUGOUT("Flow Control = " - "Rx PAUSE frames only.\r\n"); + DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); } } /* @@ -1508,7 +1504,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { hw->fc.current_mode = e1000_fc_tx_pause; - DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); + DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); } /* * For transmitting PAUSE frames ONLY. @@ -1523,14 +1519,14 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { hw->fc.current_mode = e1000_fc_rx_pause; - DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); + DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); } else { /* * Per the IEEE spec, at this point flow control * should be disabled. */ hw->fc.current_mode = e1000_fc_none; - DEBUGOUT("Flow Control = NONE.\r\n"); + DEBUGOUT("Flow Control = NONE.\n"); } /* @@ -1842,8 +1838,7 @@ s32 e1000_setup_led_generic(struct e1000_hw *hw) ledctl = E1000_READ_REG(hw, E1000_LEDCTL); hw->mac.ledctl_default = ledctl; /* Turn off LED0 */ - ledctl &= ~(E1000_LEDCTL_LED0_IVRT | - E1000_LEDCTL_LED0_BLINK | + ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | E1000_LEDCTL_LED0_MODE_MASK); ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT); @@ -2056,7 +2051,7 @@ void e1000_reset_adaptive_generic(struct e1000_hw *hw) mac->ifs_step_size = IFS_STEP; mac->ifs_ratio = IFS_RATIO; - mac->in_ifs_mode = FALSE; + mac->in_ifs_mode = false; E1000_WRITE_REG(hw, E1000_AIT, 0); out: return; @@ -2082,21 +2077,22 @@ void e1000_update_adaptive_generic(struct e1000_hw *hw) if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { if (mac->tx_packet_delta > MIN_NUM_XMITS) { - mac->in_ifs_mode = TRUE; + mac->in_ifs_mode = true; if (mac->current_ifs_val < mac->ifs_max_val) { if (!mac->current_ifs_val) mac->current_ifs_val = mac->ifs_min_val; else mac->current_ifs_val += mac->ifs_step_size; - E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); + E1000_WRITE_REG(hw, E1000_AIT, + mac->current_ifs_val); } } } else { if (mac->in_ifs_mode && (mac->tx_packet_delta <= MIN_NUM_XMITS)) { mac->current_ifs_val = 0; - mac->in_ifs_mode = FALSE; + mac->in_ifs_mode = false; E1000_WRITE_REG(hw, E1000_AIT, 0); } } @@ -2111,7 +2107,7 @@ out: * Verify that when not using auto-negotiation that MDI/MDIx is correctly * set, which is forced to MDI mode only. **/ -static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) +STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; diff --git a/lib/librte_pmd_e1000/e1000/e1000_manage.c b/lib/librte_pmd_e1000/e1000/e1000_manage.c index 5af18fe7b7..a8f911b27c 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_manage.c +++ b/lib/librte_pmd_e1000/e1000/e1000_manage.c @@ -75,7 +75,7 @@ s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_mng_enable_host_if_generic"); - if (!(hw->mac.arc_subsystem_valid)) { + if (!hw->mac.arc_subsystem_valid) { DEBUGOUT("ARC subsystem not valid.\n"); ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; goto out; @@ -83,7 +83,7 @@ s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw) /* Check that the host interface is enabled. */ hicr = E1000_READ_REG(hw, E1000_HICR); - if ((hicr & E1000_HICR_EN) == 0) { + if (!(hicr & E1000_HICR_EN)) { DEBUGOUT("E1000_HOST_EN bit disabled.\n"); ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND; goto out; @@ -110,8 +110,8 @@ out: * e1000_check_mng_mode_generic - Generic check management mode * @hw: pointer to the HW structure * - * Reads the firmware semaphore register and returns TRUE (>0) if - * manageability is enabled, else FALSE (0). + * Reads the firmware semaphore register and returns true (>0) if + * manageability is enabled, else false (0). **/ bool e1000_check_mng_mode_generic(struct e1000_hw *hw) { @@ -141,11 +141,11 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic"); - hw->mac.tx_pkt_filtering = TRUE; + hw->mac.tx_pkt_filtering = true; /* No manageability, no filtering */ if (!hw->mac.ops.check_mng_mode(hw)) { - hw->mac.tx_pkt_filtering = FALSE; + hw->mac.tx_pkt_filtering = false; goto out; } @@ -155,7 +155,7 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) */ ret_val = hw->mac.ops.mng_enable_host_if(hw); if (ret_val != E1000_SUCCESS) { - hw->mac.tx_pkt_filtering = FALSE; + hw->mac.tx_pkt_filtering = false; goto out; } @@ -437,9 +437,7 @@ s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length) * into the ram area. */ for (i = 0; i < length; i++) - E1000_WRITE_REG_ARRAY_DWORD(hw, - E1000_HOST_IF, - i, + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i, *((u32 *)buffer + i)); /* Setting this bit tells the ARC that a new command is pending. */ diff --git a/lib/librte_pmd_e1000/e1000/e1000_manage.h b/lib/librte_pmd_e1000/e1000/e1000_manage.h index 249ecca104..0265795134 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_manage.h +++ b/lib/librte_pmd_e1000/e1000/e1000_manage.h @@ -74,8 +74,7 @@ enum e1000_mng_mode { #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ -#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ - +#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI cmd limit */ #define E1000_HICR_EN 0x01 /* Enable bit - RO */ /* Driver sets this bit when done to put command in RAM */ #define E1000_HICR_C 0x02 diff --git a/lib/librte_pmd_e1000/e1000/e1000_mbx.c b/lib/librte_pmd_e1000/e1000/e1000_mbx.c index 7e544c767c..0a925dfd31 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_mbx.c +++ b/lib/librte_pmd_e1000/e1000/e1000_mbx.c @@ -37,7 +37,7 @@ POSSIBILITY OF SUCH DAMAGE. * e1000_null_mbx_check_for_flag - No-op function, return 0 * @hw: pointer to the HW structure **/ -static s32 e1000_null_mbx_check_for_flag(struct e1000_hw *hw, u16 mbx_id) +STATIC s32 e1000_null_mbx_check_for_flag(struct e1000_hw *hw, u16 mbx_id) { DEBUGFUNC("e1000_null_mbx_check_flag"); @@ -48,7 +48,7 @@ static s32 e1000_null_mbx_check_for_flag(struct e1000_hw *hw, u16 mbx_id) * e1000_null_mbx_transact - No-op function, return 0 * @hw: pointer to the HW structure **/ -static s32 e1000_null_mbx_transact(struct e1000_hw *hw, u32 *msg, u16 size, +STATIC s32 e1000_null_mbx_transact(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) { DEBUGFUNC("e1000_null_mbx_rw_msg"); @@ -174,7 +174,7 @@ s32 e1000_check_for_rst(struct e1000_hw *hw, u16 mbx_id) * * returns SUCCESS if it successfully received a message notification **/ -static s32 e1000_poll_for_msg(struct e1000_hw *hw, u16 mbx_id) +STATIC s32 e1000_poll_for_msg(struct e1000_hw *hw, u16 mbx_id) { struct e1000_mbx_info *mbx = &hw->mbx; int countdown = mbx->timeout; @@ -205,7 +205,7 @@ out: * * returns SUCCESS if it successfully received a message acknowledgement **/ -static s32 e1000_poll_for_ack(struct e1000_hw *hw, u16 mbx_id) +STATIC s32 e1000_poll_for_ack(struct e1000_hw *hw, u16 mbx_id) { struct e1000_mbx_info *mbx = &hw->mbx; int countdown = mbx->timeout; @@ -315,7 +315,7 @@ void e1000_init_mbx_ops_generic(struct e1000_hw *hw) * This function is used to read the v2p mailbox without losing the read to * clear status bits. **/ -static u32 e1000_read_v2p_mailbox(struct e1000_hw *hw) +STATIC u32 e1000_read_v2p_mailbox(struct e1000_hw *hw) { u32 v2p_mailbox = E1000_READ_REG(hw, E1000_V2PMAILBOX(0)); @@ -333,7 +333,7 @@ static u32 e1000_read_v2p_mailbox(struct e1000_hw *hw) * This function is used to check for the read to clear bits within * the V2P mailbox. **/ -static s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask) +STATIC s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask) { u32 v2p_mailbox = e1000_read_v2p_mailbox(hw); s32 ret_val = -E1000_ERR_MBX; @@ -353,7 +353,7 @@ static s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask) * * returns SUCCESS if the PF has set the Status bit or else ERR_MBX **/ -static s32 e1000_check_for_msg_vf(struct e1000_hw *hw, u16 mbx_id) +STATIC s32 e1000_check_for_msg_vf(struct e1000_hw *hw, u16 mbx_id) { s32 ret_val = -E1000_ERR_MBX; @@ -374,7 +374,7 @@ static s32 e1000_check_for_msg_vf(struct e1000_hw *hw, u16 mbx_id) * * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX **/ -static s32 e1000_check_for_ack_vf(struct e1000_hw *hw, u16 mbx_id) +STATIC s32 e1000_check_for_ack_vf(struct e1000_hw *hw, u16 mbx_id) { s32 ret_val = -E1000_ERR_MBX; @@ -393,9 +393,9 @@ static s32 e1000_check_for_ack_vf(struct e1000_hw *hw, u16 mbx_id) * @hw: pointer to the HW structure * @mbx_id: id of mailbox to check * - * returns TRUE if the PF has set the reset done bit or else FALSE + * returns true if the PF has set the reset done bit or else false **/ -static s32 e1000_check_for_rst_vf(struct e1000_hw *hw, u16 mbx_id) +STATIC s32 e1000_check_for_rst_vf(struct e1000_hw *hw, u16 mbx_id) { s32 ret_val = -E1000_ERR_MBX; @@ -416,7 +416,7 @@ static s32 e1000_check_for_rst_vf(struct e1000_hw *hw, u16 mbx_id) * * return SUCCESS if we obtained the mailbox lock **/ -static s32 e1000_obtain_mbx_lock_vf(struct e1000_hw *hw) +STATIC s32 e1000_obtain_mbx_lock_vf(struct e1000_hw *hw) { s32 ret_val = -E1000_ERR_MBX; @@ -441,7 +441,7 @@ static s32 e1000_obtain_mbx_lock_vf(struct e1000_hw *hw) * * returns SUCCESS if it successfully copied message into the buffer **/ -static s32 e1000_write_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size, +STATIC s32 e1000_write_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) { s32 ret_val; @@ -482,7 +482,7 @@ out_no_write: * * returns SUCCESS if it successfuly read message from buffer **/ -static s32 e1000_read_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size, +STATIC s32 e1000_read_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) { s32 ret_val = E1000_SUCCESS; @@ -543,7 +543,7 @@ s32 e1000_init_mbx_params_vf(struct e1000_hw *hw) return E1000_SUCCESS; } -static s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask) +STATIC s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask) { u32 mbvficr = E1000_READ_REG(hw, E1000_MBVFICR); s32 ret_val = -E1000_ERR_MBX; @@ -563,7 +563,7 @@ static s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask) * * returns SUCCESS if the VF has set the Status bit or else ERR_MBX **/ -static s32 e1000_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number) +STATIC s32 e1000_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number) { s32 ret_val = -E1000_ERR_MBX; @@ -584,7 +584,7 @@ static s32 e1000_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number) * * returns SUCCESS if the VF has set the Status bit or else ERR_MBX **/ -static s32 e1000_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number) +STATIC s32 e1000_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number) { s32 ret_val = -E1000_ERR_MBX; @@ -605,7 +605,7 @@ static s32 e1000_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number) * * returns SUCCESS if the VF has set the Status bit or else ERR_MBX **/ -static s32 e1000_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number) +STATIC s32 e1000_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number) { u32 vflre = E1000_READ_REG(hw, E1000_VFLRE); s32 ret_val = -E1000_ERR_MBX; @@ -628,7 +628,7 @@ static s32 e1000_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number) * * return SUCCESS if we obtained the mailbox lock **/ -static s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number) +STATIC s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number) { s32 ret_val = -E1000_ERR_MBX; u32 p2v_mailbox; @@ -655,7 +655,7 @@ static s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number) * * returns SUCCESS if it successfully copied message into the buffer **/ -static s32 e1000_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size, +STATIC s32 e1000_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size, u16 vf_number) { s32 ret_val; @@ -698,7 +698,7 @@ out_no_write: * memory buffer. The presumption is that the caller knows that there was * a message due to a VF request so no polling for message is needed. **/ -static s32 e1000_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size, +STATIC s32 e1000_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size, u16 vf_number) { s32 ret_val; diff --git a/lib/librte_pmd_e1000/e1000/e1000_mbx.h b/lib/librte_pmd_e1000/e1000/e1000_mbx.h index b8200d09eb..52d76f7c79 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_mbx.h +++ b/lib/librte_pmd_e1000/e1000/e1000_mbx.h @@ -61,17 +61,17 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */ /* If it's a E1000_VF_* msg then it originates in the VF and is sent to the - * PF. The reverse is TRUE if it is E1000_PF_*. + * PF. The reverse is true if it is E1000_PF_*. * Message ACK's are the value or'd with 0xF0000000 */ -#define E1000_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with - * this are the ACK */ -#define E1000_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with - * this are the NACK */ -#define E1000_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still - clear to send requests */ +/* Msgs below or'd with this are the ACK */ +#define E1000_VT_MSGTYPE_ACK 0x80000000 +/* Msgs below or'd with this are the NACK */ +#define E1000_VT_MSGTYPE_NACK 0x40000000 +/* Indicates that VF is still clear to send requests */ +#define E1000_VT_MSGTYPE_CTS 0x20000000 #define E1000_VT_MSGINFO_SHIFT 16 -/* bits 23:16 are used for exra info for certain messages */ +/* bits 23:16 are used for extra info for certain messages */ #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) #define E1000_VF_RESET 0x01 /* VF requests reset */ @@ -81,8 +81,8 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_VF_SET_MULTICAST_OVERFLOW (0x80 << E1000_VT_MSGINFO_SHIFT) #define E1000_VF_SET_VLAN 0x04 /* VF requests to set VLAN */ #define E1000_VF_SET_VLAN_ADD (0x01 << E1000_VT_MSGINFO_SHIFT) -#define E1000_VF_SET_LPE 0x05 /* VF requests to set VMOLR.LPE */ -#define E1000_VF_SET_PROMISC 0x06 /*VF requests to clear VMOLR.ROPE/MPME*/ +#define E1000_VF_SET_LPE 0x05 /* reqs to set VMOLR.LPE */ +#define E1000_VF_SET_PROMISC 0x06 /* reqs to clear VMOLR.ROPE/MPME*/ #define E1000_VF_SET_PROMISC_UNICAST (0x01 << E1000_VT_MSGINFO_SHIFT) #define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT) diff --git a/lib/librte_pmd_e1000/e1000/e1000_nvm.c b/lib/librte_pmd_e1000/e1000/e1000_nvm.c index 19fea5fd78..e2d3974034 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_nvm.c +++ b/lib/librte_pmd_e1000/e1000/e1000_nvm.c @@ -34,7 +34,7 @@ POSSIBILITY OF SUCH DAMAGE. #include "e1000_api.h" static void e1000_stop_nvm(struct e1000_hw *hw); -static void e1000_reload_nvm_generic(struct e1000_hw *hw); +STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw); /** * e1000_init_nvm_ops_generic - Initialize NVM function pointers @@ -1055,7 +1055,7 @@ out: * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the * extended control register. **/ -static void e1000_reload_nvm_generic(struct e1000_hw *hw) +STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw) { u32 ctrl_ext; diff --git a/lib/librte_pmd_e1000/e1000/e1000_osdep.h b/lib/librte_pmd_e1000/e1000/e1000_osdep.h index cf460d5d47..bf03bbf5f7 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_osdep.h +++ b/lib/librte_pmd_e1000/e1000/e1000_osdep.h @@ -125,4 +125,6 @@ static inline uint32_t e1000_read_addr(volatile void* addr) #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY +#define STATIC static + #endif /* _E1000_OSDEP_H_ */ diff --git a/lib/librte_pmd_e1000/e1000/e1000_phy.c b/lib/librte_pmd_e1000/e1000/e1000_phy.c index 381bafc431..0519b3d33a 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_phy.c +++ b/lib/librte_pmd_e1000/e1000/e1000_phy.c @@ -546,7 +546,7 @@ out: **/ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) { - return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); + return __e1000_read_phy_reg_igp(hw, offset, data, false); } /** @@ -560,7 +560,7 @@ s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) **/ s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) { - return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); + return __e1000_read_phy_reg_igp(hw, offset, data, true); } /** @@ -619,7 +619,7 @@ out: **/ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) { - return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); + return __e1000_write_phy_reg_igp(hw, offset, data, false); } /** @@ -633,7 +633,7 @@ s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) **/ s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) { - return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); + return __e1000_write_phy_reg_igp(hw, offset, data, true); } /** @@ -692,7 +692,7 @@ out: **/ s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) { - return __e1000_read_kmrn_reg(hw, offset, data, FALSE); + return __e1000_read_kmrn_reg(hw, offset, data, false); } /** @@ -707,7 +707,7 @@ s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) **/ s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) { - return __e1000_read_kmrn_reg(hw, offset, data, TRUE); + return __e1000_read_kmrn_reg(hw, offset, data, true); } /** @@ -762,7 +762,7 @@ out: **/ s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) { - return __e1000_write_kmrn_reg(hw, offset, data, FALSE); + return __e1000_write_kmrn_reg(hw, offset, data, false); } /** @@ -776,7 +776,7 @@ s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) **/ s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) { - return __e1000_write_kmrn_reg(hw, offset, data, TRUE); + return __e1000_write_kmrn_reg(hw, offset, data, true); } /** @@ -1421,10 +1421,8 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) * Check link status. Wait up to 100 microseconds for link to become * valid. */ - ret_val = e1000_phy_has_link_generic(hw, - COPPER_LINK_UP_LIMIT, - 10, - &link); + ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, + &link); if (ret_val) goto out; @@ -1489,10 +1487,8 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) if (phy->autoneg_wait_to_complete) { DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); - ret_val = e1000_phy_has_link_generic(hw, - PHY_FORCE_LIMIT, - 100000, - &link); + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); if (ret_val) goto out; @@ -1690,12 +1686,8 @@ s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) DEBUGOUT("Link taking longer than expected.\n"); /* Try once more */ - ret_val = e1000_phy_has_link_generic(hw, - PHY_FORCE_LIMIT, - 100000, - &link); - if (ret_val) - goto out; + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, + 100000, &link); } out: @@ -1772,7 +1764,7 @@ void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) * Success returns 0, Failure returns 1 * * The low power link up (lplu) state is set to the power management level D3 - * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 + * and SmartSpeed is disabled when active is true, else clear lplu for D3 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU * is used during Dx states where the power conservation is most important. * During driver activity, SmartSpeed should be enabled so performance is @@ -1885,7 +1877,7 @@ s32 e1000_check_downshift_generic(struct e1000_hw *hw) break; default: /* speed downshift not supported */ - phy->speed_downgraded = FALSE; + phy->speed_downgraded = false; ret_val = E1000_SUCCESS; goto out; } @@ -1893,7 +1885,7 @@ s32 e1000_check_downshift_generic(struct e1000_hw *hw) ret_val = phy->ops.read_reg(hw, offset, &phy_data); if (!ret_val) - phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; + phy->speed_downgraded = !!(phy_data & mask); out: return ret_val; @@ -2023,7 +2015,7 @@ s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_wait_autoneg_generic"); - if (!(hw->phy.ops.read_reg)) + if (!hw->phy.ops.read_reg) return E1000_SUCCESS; /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ @@ -2063,7 +2055,7 @@ s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, DEBUGFUNC("e1000_phy_has_link_generic"); - if (!(hw->phy.ops.read_reg)) + if (!hw->phy.ops.read_reg) return E1000_SUCCESS; for (i = 0; i < iterations; i++) { @@ -2091,7 +2083,7 @@ s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, usec_delay(usec_interval); } - *success = (i < iterations) ? TRUE : FALSE; + *success = (i < iterations); return ret_val; } @@ -2178,12 +2170,13 @@ s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) phy->max_cable_length = phy_data / (is_cm ? 100 : 1); phy->cable_length = phy_data / (is_cm ? 100 : 1); - /* Reset the page selec to its original value */ + /* Reset the page select to its original value */ ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, default_page); if (ret_val) goto out; break; + case M88E1112_E_PHY_ID: /* Remember the original page select and set it to 5 */ ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, @@ -2343,8 +2336,8 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) if (ret_val) goto out; - phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) - ? TRUE : FALSE; + phy->polarity_correction = !!(phy_data & + M88E1000_PSCR_POLARITY_REVERSAL); ret_val = e1000_check_polarity_m88(hw); if (ret_val) @@ -2354,7 +2347,7 @@ s32 e1000_get_phy_info_m88(struct e1000_hw *hw) if (ret_val) goto out; - phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; + phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { ret_val = hw->phy.ops.get_cable_length(hw); @@ -2411,7 +2404,7 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw) goto out; } - phy->polarity_correction = TRUE; + phy->polarity_correction = true; ret_val = e1000_check_polarity_igp(hw); if (ret_val) @@ -2421,7 +2414,7 @@ s32 e1000_get_phy_info_igp(struct e1000_hw *hw) if (ret_val) goto out; - phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; + phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); if ((data & IGP01E1000_PSSR_SPEED_MASK) == IGP01E1000_PSSR_SPEED_1000MBPS) { @@ -2496,7 +2489,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw) if (ret_val) goto out; - phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; + phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); /* The following parameters are undefined for 10/100 operation. */ phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; diff --git a/lib/librte_pmd_e1000/e1000/e1000_regs.h b/lib/librte_pmd_e1000/e1000/e1000_regs.h index 93b39a159a..3ba900f14a 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_regs.h +++ b/lib/librte_pmd_e1000/e1000/e1000_regs.h @@ -103,11 +103,11 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ #define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */ -#define E1000_ICR_V2 0x01500 /* Interrupt Cause - new location - RC */ -#define E1000_ICS_V2 0x01504 /* Interrupt Cause Set - new location - WO */ -#define E1000_IMS_V2 0x01508 /* Interrupt Mask Set/Read - new location - RW */ -#define E1000_IMC_V2 0x0150C /* Interrupt Mask Clear - new location - WO */ -#define E1000_IAM_V2 0x01510 /* Interrupt Ack Auto Mask - new location - RW */ +#define E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */ +#define E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */ +#define E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */ +#define E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */ +#define E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */ #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ @@ -191,24 +191,26 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) -#define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */ -#define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Packet Buffer DWORD (_n) */ +#define E1000_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */ +#define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */ #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ -#define E1000_ITPBS 0x03404 /* Same as TXPBS, renamed for newer adpaters - RW */ +/* Same as TXPBS, renamed for newer Si - RW */ +#define E1000_ITPBS 0x03404 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ -#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ -#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ -#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ -#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */ -#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */ +#define E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */ +#define E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */ +#define E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */ +#define E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */ +#define E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */ #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */ #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */ -#define E1000_DTXMXSZRQ 0x03540 /* DMA Tx Max Total Allow Size Requests - RW */ +/* DMA Tx Max Total Allow Size Reqs - RW */ +#define E1000_DTXMXSZRQ 0x03540 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ @@ -300,55 +302,61 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n))) #define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n))) -#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */ -#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */ -#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */ -#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */ -#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */ -#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */ -#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */ -#define E1000_LSECRXOCTV 0x04320 /* LinkSec Rx Octets Validated - InOctetsValidated */ -#define E1000_LSECRXBAD 0x04324 /* LinkSec Rx Bad Tag - InPktsBadTag */ -#define E1000_LSECRXNOSCI 0x04328 /* LinkSec Rx Packet No SCI Count - InPktsNoSci */ -#define E1000_LSECRXUNSCI 0x0432C /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */ -#define E1000_LSECRXUNCH 0x04330 /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */ -#define E1000_LSECRXDELAY 0x04340 /* LinkSec Rx Delayed Packet Count - InPktsDelayed */ -#define E1000_LSECRXLATE 0x04350 /* LinkSec Rx Late Packets Count - InPktsLate */ -#define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */ -#define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */ -#define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */ -#define E1000_LSECRXUNSA 0x043C0 /* LinkSec Rx Unused SA Count - InPktsUnusedSa */ -#define E1000_LSECRXNUSA 0x043D0 /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */ -#define E1000_LSECTXCAP 0x0B000 /* LinkSec Tx Capabilities Register - RO */ -#define E1000_LSECRXCAP 0x0B300 /* LinkSec Rx Capabilities Register - RO */ -#define E1000_LSECTXCTRL 0x0B004 /* LinkSec Tx Control - RW */ -#define E1000_LSECRXCTRL 0x0B304 /* LinkSec Rx Control - RW */ -#define E1000_LSECTXSCL 0x0B008 /* LinkSec Tx SCI Low - RW */ -#define E1000_LSECTXSCH 0x0B00C /* LinkSec Tx SCI High - RW */ -#define E1000_LSECTXSA 0x0B010 /* LinkSec Tx SA0 - RW */ -#define E1000_LSECTXPN0 0x0B018 /* LinkSec Tx SA PN 0 - RW */ -#define E1000_LSECTXPN1 0x0B01C /* LinkSec Tx SA PN 1 - RW */ -#define E1000_LSECRXSCL 0x0B3D0 /* LinkSec Rx SCI Low - RW */ -#define E1000_LSECRXSCH 0x0B3E0 /* LinkSec Rx SCI High - RW */ -#define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */ -#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */ -#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */ -#define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */ +/* LinkSec */ +#define E1000_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */ +#define E1000_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */ +#define E1000_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */ +#define E1000_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */ +#define E1000_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */ +#define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */ +#define E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */ +#define E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */ +#define E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */ +#define E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */ +#define E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */ +#define E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */ +#define E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */ +#define E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */ +#define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */ +#define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */ +#define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */ +#define E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */ +#define E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */ +#define E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */ +#define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */ +#define E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */ +#define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */ +#define E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */ +#define E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */ +#define E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */ +#define E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */ +#define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */ +#define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */ +#define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */ +/* LinkSec Tx 128-bit Key 0 - WO */ +#define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) +/* LinkSec Tx 128-bit Key 1 - WO */ +#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) +#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */ +#define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */ /* * LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit * key - RW. */ #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) -#define E1000_SSVPC 0x041A0 /* Switch Security Violation Packet Count */ +#define E1000_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */ #define E1000_IPSCTRL 0xB430 /* IpSec Control Register */ #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */ #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */ -#define E1000_IPSRXIPADDR(_n) (0x0B420+ (0x04 * (_n))) /* IPSec Rx IPv4/v6 Address - RW */ -#define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */ +/* IPSec Rx IPv4/v6 Address - RW */ +#define E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n))) +/* IPSec Rx 128-bit Key - RW */ +#define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */ #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */ -#define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */ +/* IPSec Tx 128-bit Key - RW */ +#define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) #define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */ #define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */ #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ @@ -371,16 +379,18 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ -#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ -#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ +#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */ +#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */ #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ #define E1000_RA 0x05400 /* Receive Address - RW Array */ -#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */ +#define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ +#define E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */ +#define E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */ #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ #define E1000_WUC 0x05800 /* Wakeup Control - RW */ @@ -397,15 +407,18 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_HOST_IF 0x08800 /* Host Interface */ #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ -#define E1000_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */ -#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */ +/* Flexible Host Filter Table */ +#define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100)) +/* Ext Flexible Host Filter Table */ +#define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100)) #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ #define E1000_MDPHYA 0x0003C /* PHY address - RW */ #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ -#define E1000_MDEF(_n) (0x05890 + (4 * (_n))) /* Mngmt Decision Filters */ -#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ +/* Management Decision Filters */ +#define E1000_MDEF(_n) (0x05890 + (4 * (_n))) +#define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ @@ -418,7 +431,8 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ #define E1000_SWSM 0x05B50 /* SW Semaphore */ #define E1000_FWSM 0x05B54 /* FW Semaphore */ -#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ +/* Driver-only SW semaphore (not used by BOOT agents) */ +#define E1000_SWSM2 0x05B58 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ #define E1000_UFUSE 0x05B78 /* UFUSE - RO */ @@ -430,18 +444,17 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ -#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ -#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */ -#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register - * (_i) - RW */ -#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr - * low reg - RW */ -#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr - * upper reg - RW */ -#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry - * message reg - RW */ -#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry - * vector ctrl reg - RW */ +#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ +#define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */ +#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */ +/* MSI-X Table entry addr low reg - RW */ +#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) +/* MSI-X Table entry addr upper reg - RW */ +#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) +/* MSI-X Table entry message reg - RW */ +#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) +/* MSI-X Table entry vector ctrl reg - RW */ +#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) #define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ @@ -475,8 +488,8 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) #define E1000_VFVMBMEM(_n) (0x00800 + (_n)) #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) -#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine - * Filter - RW */ +/* VLAN Virtual Machine Filter - RW */ +#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) #define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) #define E1000_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */ /* Time Sync */ @@ -509,17 +522,28 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */ #define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ #define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ -#define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */ -#define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */ -#define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */ -#define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */ -#define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */ -#define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */ -#define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */ -#define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */ -#define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */ -#define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/ -#define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */ +/* Tx Desc plane TC Rate-scheduler config */ +#define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) +/* Tx Packet plane TC Rate-Scheduler Config */ +#define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) +/* Rx Packet plane TC Rate-Scheduler Config */ +#define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) +/* Tx Desc Plane TC Rate-Scheduler Status */ +#define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) +/* Tx Desc Plane TC Rate-Scheduler MMW */ +#define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) +/* Tx Packet plane TC Rate-Scheduler Status */ +#define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) +/* Tx Packet plane TC Rate-scheduler MMW */ +#define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) +/* Rx Packet plane TC Rate-Scheduler Status */ +#define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) +/* Rx Packet plane TC Rate-Scheduler MMW */ +#define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) +/* Tx Desc plane VM Rate-Scheduler MMW*/ +#define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) +/* Tx BCN Rate-Scheduler MMW */ +#define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */ #define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */ #define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */ @@ -556,7 +580,7 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_THHIGHTC 0x0810C /* High Threshold Control */ #define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ -/*Energy Efficient Ethernet "EEE" registers */ +/* Energy Efficient Ethernet "EEE" registers */ #define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ #define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ #define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/ @@ -570,4 +594,6 @@ POSSIBILITY OF SUCH DAMAGE. #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ + + #endif diff --git a/lib/librte_pmd_e1000/e1000/e1000_vf.c b/lib/librte_pmd_e1000/e1000/e1000_vf.c index 3984c1a7ea..b3a6b01440 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_vf.c +++ b/lib/librte_pmd_e1000/e1000/e1000_vf.c @@ -35,21 +35,21 @@ POSSIBILITY OF SUCH DAMAGE. #include "e1000_api.h" -static s32 e1000_init_phy_params_vf(struct e1000_hw *hw); -static s32 e1000_init_nvm_params_vf(struct e1000_hw *hw); -static void e1000_release_vf(struct e1000_hw *hw); -static s32 e1000_acquire_vf(struct e1000_hw *hw); -static s32 e1000_setup_link_vf(struct e1000_hw *hw); -static s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw); -static s32 e1000_init_mac_params_vf(struct e1000_hw *hw); -static s32 e1000_check_for_link_vf(struct e1000_hw *hw); -static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed, +STATIC s32 e1000_init_phy_params_vf(struct e1000_hw *hw); +STATIC s32 e1000_init_nvm_params_vf(struct e1000_hw *hw); +STATIC void e1000_release_vf(struct e1000_hw *hw); +STATIC s32 e1000_acquire_vf(struct e1000_hw *hw); +STATIC s32 e1000_setup_link_vf(struct e1000_hw *hw); +STATIC s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw); +STATIC s32 e1000_init_mac_params_vf(struct e1000_hw *hw); +STATIC s32 e1000_check_for_link_vf(struct e1000_hw *hw); +STATIC s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed, u16 *duplex); -static s32 e1000_init_hw_vf(struct e1000_hw *hw); -static s32 e1000_reset_hw_vf(struct e1000_hw *hw); -static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32); -static void e1000_rar_set_vf(struct e1000_hw *, u8 *, u32); -static s32 e1000_read_mac_addr_vf(struct e1000_hw *); +STATIC s32 e1000_init_hw_vf(struct e1000_hw *hw); +STATIC s32 e1000_reset_hw_vf(struct e1000_hw *hw); +STATIC void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32); +STATIC void e1000_rar_set_vf(struct e1000_hw *, u8 *, u32); +STATIC s32 e1000_read_mac_addr_vf(struct e1000_hw *); /** * e1000_init_phy_params_vf - Inits PHY params @@ -57,7 +57,7 @@ static s32 e1000_read_mac_addr_vf(struct e1000_hw *); * * Doesn't do much - there's no PHY available to the VF. **/ -static s32 e1000_init_phy_params_vf(struct e1000_hw *hw) +STATIC s32 e1000_init_phy_params_vf(struct e1000_hw *hw) { DEBUGFUNC("e1000_init_phy_params_vf"); hw->phy.type = e1000_phy_vf; @@ -73,7 +73,7 @@ static s32 e1000_init_phy_params_vf(struct e1000_hw *hw) * * Doesn't do much - there's no NVM available to the VF. **/ -static s32 e1000_init_nvm_params_vf(struct e1000_hw *hw) +STATIC s32 e1000_init_nvm_params_vf(struct e1000_hw *hw) { DEBUGFUNC("e1000_init_nvm_params_vf"); hw->nvm.type = e1000_nvm_none; @@ -87,7 +87,7 @@ static s32 e1000_init_nvm_params_vf(struct e1000_hw *hw) * e1000_init_mac_params_vf - Inits MAC params * @hw: pointer to the HW structure **/ -static s32 e1000_init_mac_params_vf(struct e1000_hw *hw) +STATIC s32 e1000_init_mac_params_vf(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; @@ -102,11 +102,11 @@ static s32 e1000_init_mac_params_vf(struct e1000_hw *hw) hw->phy.media_type = e1000_media_type_unknown; /* No ASF features for the VF driver */ - mac->asf_firmware_present = FALSE; + mac->asf_firmware_present = false; /* ARC subsystem not supported */ - mac->arc_subsystem_valid = FALSE; + mac->arc_subsystem_valid = false; /* Disable adaptive IFS mode so the generic funcs don't do anything */ - mac->adaptive_ifs = FALSE; + mac->adaptive_ifs = false; /* VF's have no MTA Registers - PF feature only */ mac->mta_reg_count = 128; /* VF's have no access to RAR entries */ @@ -158,7 +158,7 @@ void e1000_init_function_pointers_vf(struct e1000_hw *hw) * In addition, the MAC registers to access PHY/NVM don't exist so we don't * even want any SW to attempt to use them. **/ -static s32 e1000_acquire_vf(struct e1000_hw *hw) +STATIC s32 e1000_acquire_vf(struct e1000_hw *hw) { return -E1000_ERR_PHY; } @@ -171,7 +171,7 @@ static s32 e1000_acquire_vf(struct e1000_hw *hw) * In addition, the MAC registers to access PHY/NVM don't exist so we don't * even want any SW to attempt to use them. **/ -static void e1000_release_vf(struct e1000_hw *hw) +STATIC void e1000_release_vf(struct e1000_hw *hw) { return; } @@ -182,7 +182,7 @@ static void e1000_release_vf(struct e1000_hw *hw) * * Virtual functions cannot change link. **/ -static s32 e1000_setup_link_vf(struct e1000_hw *hw) +STATIC s32 e1000_setup_link_vf(struct e1000_hw *hw) { DEBUGFUNC("e1000_setup_link_vf"); @@ -195,7 +195,7 @@ static s32 e1000_setup_link_vf(struct e1000_hw *hw) * * Virtual functions are not really on their own bus. **/ -static s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw) +STATIC s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw) { struct e1000_bus_info *bus = &hw->bus; @@ -217,7 +217,7 @@ static s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw) * Since we cannot read the PHY and get accurate link info, we must rely upon * the status register's data which is often stale and inaccurate. **/ -static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed, +STATIC s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed, u16 *duplex) { s32 status; @@ -254,7 +254,7 @@ static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed, * VF's provide a function level reset. This is done using bit 26 of ctrl_reg. * This is all the reset we can perform on a VF. **/ -static s32 e1000_reset_hw_vf(struct e1000_hw *hw) +STATIC s32 e1000_reset_hw_vf(struct e1000_hw *hw) { struct e1000_mbx_info *mbx = &hw->mbx; u32 timeout = E1000_VF_INIT_TIMEOUT; @@ -303,7 +303,7 @@ static s32 e1000_reset_hw_vf(struct e1000_hw *hw) * * Not much to do here except clear the PF Reset indication if there is one. **/ -static s32 e1000_init_hw_vf(struct e1000_hw *hw) +STATIC s32 e1000_init_hw_vf(struct e1000_hw *hw) { DEBUGFUNC("e1000_init_hw_vf"); @@ -319,7 +319,7 @@ static s32 e1000_init_hw_vf(struct e1000_hw *hw) * @addr: pointer to the receive address * @index receive address array register **/ -static void e1000_rar_set_vf(struct e1000_hw *hw, u8 * addr, u32 index) +STATIC void e1000_rar_set_vf(struct e1000_hw *hw, u8 * addr, u32 index) { struct e1000_mbx_info *mbx = &hw->mbx; u32 msgbuf[3]; @@ -350,7 +350,7 @@ static void e1000_rar_set_vf(struct e1000_hw *hw, u8 * addr, u32 index) * Generates a multicast address hash value which is used to determine * the multicast filter table array address and new table value. **/ -static u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr) +STATIC u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr) { u32 hash_value, hash_mask; u8 bit_shift = 0; @@ -498,7 +498,7 @@ s32 e1000_promisc_set_vf(struct e1000_hw *hw, enum e1000_promisc_type type) * e1000_read_mac_addr_vf - Read device MAC address * @hw: pointer to the HW structure **/ -static s32 e1000_read_mac_addr_vf(struct e1000_hw *hw) +STATIC s32 e1000_read_mac_addr_vf(struct e1000_hw *hw) { int i; @@ -516,7 +516,7 @@ static s32 e1000_read_mac_addr_vf(struct e1000_hw *hw) * if it is then it reports the link state to the hardware, otherwise * it reports link down and returns an error. **/ -static s32 e1000_check_for_link_vf(struct e1000_hw *hw) +STATIC s32 e1000_check_for_link_vf(struct e1000_hw *hw) { struct e1000_mbx_info *mbx = &hw->mbx; struct e1000_mac_info *mac = &hw->mac; @@ -533,7 +533,7 @@ static s32 e1000_check_for_link_vf(struct e1000_hw *hw) /* If we were hit with a reset or timeout drop the link */ if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) - mac->get_link_status = TRUE; + mac->get_link_status = true; if (!mac->get_link_status) goto out; @@ -565,7 +565,7 @@ static s32 e1000_check_for_link_vf(struct e1000_hw *hw) /* if we passed all the tests above then the link is up and we no * longer need to check for link */ - mac->get_link_status = FALSE; + mac->get_link_status = false; out: return ret_val; diff --git a/lib/librte_pmd_e1000/e1000/e1000_vf.h b/lib/librte_pmd_e1000/e1000/e1000_vf.h index fe5a72bf50..716bb73000 100644 --- a/lib/librte_pmd_e1000/e1000/e1000_vf.h +++ b/lib/librte_pmd_e1000/e1000/e1000_vf.h @@ -43,11 +43,11 @@ struct e1000_hw; #define E1000_DEV_ID_82576_VF 0x10CA #define E1000_DEV_ID_I350_VF 0x1520 -#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ +#define E1000_VF_INIT_TIMEOUT 200 /* Num of retries to clear RSTI */ /* Additional Descriptor Control definitions */ -#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ -#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ +#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ +#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ /* SRRCTL bit definitions */ #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ @@ -68,13 +68,13 @@ struct e1000_hw; /* Interrupt Defines */ #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ #define E1000_EITR(_n) (0x01680 + ((_n) << 2)) -#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ -#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ -#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ -#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ -#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ -#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ -#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ +#define E1000_EICS 0x01520 /* Ext. Intr Cause Set -W0 */ +#define E1000_EIMS 0x01524 /* Ext. Intr Mask Set/Read -RW */ +#define E1000_EIMC 0x01528 /* Ext. Intr Mask Clear -WO */ +#define E1000_EIAC 0x0152C /* Ext. Intr Auto Clear -RW */ +#define E1000_EIAM 0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */ +#define E1000_IVAR0 0x01700 /* Intr Vector Alloc (array) -RW */ +#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes -RW */ #define E1000_IVAR_VALID 0x80 /* Receive Descriptor - Advanced */ @@ -156,7 +156,7 @@ enum e1000_mac_type { e1000_undefined = 0, e1000_vfadapt, e1000_vfadapt_i350, - e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ + e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ }; struct e1000_vf_stats {